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VLSI LAYOUT USING REDUNDANT NODES TO INCREASE THE RELIABILITY
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VLSI LAYOUT USING REDUNDANT NODES TO INCREASE THE RELIABILITY
ORDINARY APPLICATION
Published
Filed on 8 February 2023
Patent Information
| Application ID | 202341008225 |
| Date of Application | 08/02/2023 |
Documents
| Name | Date |
|---|---|
| 202341008225-COMPLETE SPECIFICATION [08-02-2023(online)].pdf | 08/02/2023 |
| 202341008225-DECLARATION OF INVENTORSHIP (FORM 5) [08-02-2023(online)].pdf | 08/02/2023 |
| 202341008225-DRAWINGS [08-02-2023(online)].pdf | 08/02/2023 |
| 202341008225-FORM 1 [08-02-2023(online)].pdf | 08/02/2023 |
| 202341008225-FORM-9 [08-02-2023(online)].pdf | 08/02/2023 |
| 202341008225-REQUEST FOR EARLY PUBLICATION(FORM-9) [08-02-2023(online)].pdf | 08/02/2023 |
