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VERTICALLY-ALIGNED CONDUCTIVE DUMMIES IN INTEGRATED CIRCUIT LAYERS FOR CAPACITANCE REDUCTION AND BIAS INDEPENDENCE AND METHODS OF MANUFACTURE
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Abstract
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VERTICALLY-ALIGNED CONDUCTIVE DUMMIES IN INTEGRATED CIRCUIT LAYERS FOR CAPACITANCE REDUCTION AND BIAS INDEPENDENCE AND METHODS OF MANUFACTURE
PCT NATIONAL PHASE APPLICATION
Published
Filed on 23 August 2022
Patent Information
| Application ID | 202247047901 |
| Date of Application | 23/08/2022 |
Documents
| Name | Date |
|---|---|
| 202247047901-FORM 3 [14-02-2023(online)].pdf | 14/02/2023 |
| 202247047901-FORM 3 [22-11-2022(online)].pdf | 22/11/2022 |
| 202247047901-Proof of Right [22-11-2022(online)].pdf | 22/11/2022 |
| 202247047901-COMPLETE SPECIFICATION [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-DECLARATION OF INVENTORSHIP (FORM 5) [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-DRAWINGS [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-FORM 1 [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-POWER OF AUTHORITY [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-PRIORITY DOCUMENTS [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-STATEMENT OF UNDERTAKING (FORM 3) [23-08-2022(online)].pdf | 23/08/2022 |
| 202247047901-TRANSLATIOIN OF PRIOIRTY DOCUMENTS ETC. [23-08-2022(online)].pdf | 23/08/2022 |
