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Vedic-Mathematics based Effective High- Speed and Low Power Multiplier Architecture using for DSP Application
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Abstract
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Vedic-Mathematics based Effective High- Speed and Low Power Multiplier Architecture using for DSP Application
ORDINARY APPLICATION
Published
Filed on 22 January 2022
Patent Information
| Application ID | 202241003733 |
| Date of Application | 22/01/2022 |
Documents
| Name | Date |
|---|---|
| 202241003733-COMPLETE SPECIFICATION [22-01-2022(online)].pdf | 22/01/2022 |
| 202241003733-DECLARATION OF INVENTORSHIP (FORM 5) [22-01-2022(online)].pdf | 22/01/2022 |
| 202241003733-DRAWINGS [22-01-2022(online)].pdf | 22/01/2022 |
| 202241003733-FORM 1 [22-01-2022(online)].pdf | 22/01/2022 |
| 202241003733-FORM-9 [22-01-2022(online)].pdf | 22/01/2022 |
| 202241003733-POWER OF AUTHORITY [22-01-2022(online)].pdf | 22/01/2022 |
| 202241003733-REQUEST FOR EARLY PUBLICATION(FORM-9) [22-01-2022(online)].pdf | 22/01/2022 |
