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U-Shape Spacer Junctionless field-effect transistor (JLFET)
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ORDINARY APPLICATION
Published
Filed on 14 November 2024
Abstract
A novel U-Shape Spacer Junctionless field-effect transistor (JLFET) is disclosed, featuring a silicon nanowire channel with a graded doping profile, a high-k gate dielectric, and a dual-metal gate structure. This innovative design addresses the challenges of leakage currents and short-channel effects in advanced semiconductor devices, particularly those operating at sub-10nm technology nodes. The graded doping profile enhances carrier mobility and reduces off-state leakage, thereby improving the overall efficiency of the transistor. The high-k gate dielectric minimizes gate leakage and improves gate control, contributing to the device's high performance. The dual-metal gate structure provides optimal threshold voltage control, ensuring stable and reliable operation. As a result, this U-Shape Spacer JLFET design offers significant advantages in terms of device performance, energy efficiency, and scalability. This advanced transistor is particularly suited for next-generation high-performance and low-power electronic applications, offering substantial improvements in both operational speed and power consumption. Additionally, the novel design facilitates easier integration into existing semiconductor manufacturing processes, making it highly viable for commercial applications.
Patent Information
Application ID | 202431087934 |
Invention Field | ELECTRONICS |
Date of Application | 14/11/2024 |
Publication Number | 47/2024 |
Inventors
Name | Address | Country | Nationality |
---|---|---|---|
Rikhit Swargiary | Vill:Dhupguri, PO:Goraibari | India | India |
Dr Kaushik Deva Sarma | Department of Instrumentation Engineering, P.O. & District- Kokrajhar, Bodoland Territorial Region, Assam - 783370, India | India | India |
Anjanmani Baro | Vill:Kharuajan, PO:Kharua | India | India |
Namita Das | Department of Electronic and Communication Engineering P.O. & District- Kokrajhar, Bodoland Territorial Region, Assam - 783370, India | India | India |
Applicants
Name | Address | Country | Nationality |
---|---|---|---|
Rikhit Swargiary | Vill:Dhupguri, PO:Goraibari | India | India |
Dr Kaushik Deva Sarma | Department of Instrumentation Engineering, P.O. & District- Kokrajhar, Bodoland Territorial Region, Assam - 783370, India | India | India |
Anjanmani Baro | Vill:Kharuajan, PO:Kharua | India | India |
Namita Das | Department of Electronic and Communication Engineering P.O. & District- Kokrajhar, Bodoland Territorial Region, Assam - 783370, India | India | India |
Specification
Description:Description:
Construction and Operation of the U-Shape Spacer JLFET:
The U-Shape Spacer JLFET is a type of transistor that differs from traditional MOSFETs primarily in its structure and the absence of PN-junctions. Here's a detailed look at its construction:
• Channel Region: The core feature of a U-Shape Spacer JLFET is its channel region, which is uniformly doped with a single type of dopant, either n-type or p-type, throughout the entire channel. This contrasts with conventional FETs that use different dopant types to form junctions. The channel is typically made of silicon, but other materials like germanium or compound semiconductors can also be used.
• Gate Structure: The gate in a U-shaped spacer JLFET is similar to that in a MOSFET, being situated above the channel region and separated by a thin gate dielectric layer. This gate dielectric is usually made from materials like silicon dioxide (SiO2) or high-k materials such as hafnium oxide (HfO2), which serve to insulate the gate from the channel.
• Source and Drain: The source and drain regions are connected to the channel and are doped with the same type of impurity as the channel itself. These regions are located at the ends of the channel, facilitating the flow of current when the transistor is in operation.
• Gate Dielectric: The gate dielectric layer is crucial for controlling the electrostatic potential of the channel and is engineered to have a high dielectric constant (high-k) in advanced designs to improve performance.
• U-shaped spacer: The spacer is a dielectric layer adjacent to the gate dielectric layer. It is placed over the source-drain region to create a fringing field for better analogue performance. In this design, the shape of the spacer is like the letter "U".
Materials Used:
• Semiconductor Material: The channel material is usually silicon but can be substituted with other semiconductors depending on the desired electrical characteristics. For high-performance applications, materials such as germanium or compound semiconductors (e.g., gallium arsenide) is used.
• Gate Dielectric: The gate dielectric is often silicon dioxide or a high-k material. High-k dielectrics, like hafnium oxide (HfO2), are used to enhance gate capacitance and reduce leakage currents.
• Dopants: Uniform doping is achieved using standard techniques like ion implantation or diffusion. For N-type JLFETs, dopants such as phosphorus or arsenic are used, while for P-type JLFETs, boron or gallium is employed.
• Spacer: The spacer is a high-k material. High-k dielectrics, like hafnium oxide.
The Figure 1 shows cross-sectional view of the U-Shape Spacer JLFET and the specifications of the U-Shape Spacer JLFET structure are considered fixed throughout all the simulations shown in Table 1.
Operation:
The operation of a U-Shape Spacer JLFET is governed by the electrostatic control exerted by the gate over the channel region:
• Off-State: When the gate voltage is below the threshold, the channel remains in a high-resistance state. The channel region is fully depleted and because of the spacer the depletion in channel extends in the source-drain region also. The depletion layer. The mode of operation in off-state is called subthreshold mode as shown in Figure 2.
• On-State: The on-state of the device has three modes. When the gate voltage exceeds the threshold voltage, the depletion layer in the channel starts to convert back in to neutral semiconductor layer. This mode of operation is termed as bulk current mode. In this mode on current starts flowing through the bulk of the device. With rise in gate voltage the current rises and it reaches flat band and accumulation mode where a very large current flows through the device. The three modes of operation of the on state of the device as shown in Figure 3-5. , Claims:[1]. A U-Shape Spacer Junctionless field-effect transistor (JLFET) comprising: A silicon nanowire channel with a graded doping profile from the source to the drain, a high-k gate dielectric material surrounding the nanowire channel and a dual-metal gate structure positioned over the gate dielectric for optimal threshold voltage control.
[2]. The U-Shape Spacer JLFET as claimed in claim 1, wherein the graded doping profile enhances carrier mobility and reduces off-state leakage currents.
[3]. The U-Shape Spacer JLFET as claimed in claim 1, wherein the high-k gate dielectric material is selected from a group consisting of hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and aluminum oxide (Al₂O₃).
[4]. The U-Shape Spacer JLFET as claimed in claim 1, wherein the nanowire channel has a diameter in the range of 5 nm to 20 nm.
[5]. The U-Shape Spacer JLFET as claimed in claim 1, wherein the dual-metal gate structure includes a combination of metals selected from the group consisting of titanium (Ti), aluminum (Al), tungsten (W), and cobalt (Co).
Documents
Name | Date |
---|---|
202431087934-COMPLETE SPECIFICATION [14-11-2024(online)].pdf | 14/11/2024 |
202431087934-DRAWINGS [14-11-2024(online)].pdf | 14/11/2024 |
202431087934-FORM 1 [14-11-2024(online)].pdf | 14/11/2024 |
202431087934-REQUEST FOR EARLY PUBLICATION(FORM-9) [14-11-2024(online)].pdf | 14/11/2024 |
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