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STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELL CIRCUITS WITH A MINIMUM DISTANCE BETWEEN A STORAGE CIRCUIT ACTIVE REGION AND A READ PORT CIRCUIT ACTIVE REGION TO REDUCE AREA AND SRAM BIT CELL ARRAY CIRCUITS
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Abstract
Information
Inventors
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Specification
Documents
STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELL CIRCUITS WITH A MINIMUM DISTANCE BETWEEN A STORAGE CIRCUIT ACTIVE REGION AND A READ PORT CIRCUIT ACTIVE REGION TO REDUCE AREA AND SRAM BIT CELL ARRAY CIRCUITS
PCT NATIONAL PHASE APPLICATION
Published
Filed on 6 February 2023
Patent Information
| Application ID | 202347007422 |
| Date of Application | 06/02/2023 |
Documents
| Name | Date |
|---|---|
| 202347007422-FORM 3 [24-07-2023(online)].pdf | 24/07/2023 |
| 202347007422-Proof of Right [03-04-2023(online)].pdf | 03/04/2023 |
| 202347007422-COMPLETE SPECIFICATION [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-DECLARATION OF INVENTORSHIP (FORM 5) [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-DRAWINGS [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-FORM 1 [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-POWER OF AUTHORITY [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-PRIORITY DOCUMENTS [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-STATEMENT OF UNDERTAKING (FORM 3) [06-02-2023(online)].pdf | 06/02/2023 |
| 202347007422-TRANSLATIOIN OF PRIOIRTY DOCUMENTS ETC. [06-02-2023(online)].pdf | 06/02/2023 |
