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ROBUST HALFBRIDGE

PCT NATIONAL PHASE APPLICATION

Published

date

Filed on 21 November 2024

Abstract

A semiconductor transistor comprising: a drain region; a plurality of source regions; and a plurality of gate regions interleaved with the source regions.

Patent Information

Application ID202447090709
Invention FieldELECTRONICS
Date of Application21/11/2024
Publication Number48/2024

Inventors

NameAddressCountryNationality
VEPRINSKY, Valery16 HaPalmah Street 6706530 Tel AvivIsraelIsrael
ROITER, Yulia5 Sitrin 7706705 AshdodIsraelIsrael
SHERMAN, DanielC/O Visic Technologies Ltd. 7 Golda Meir 7403650 Ness ZionaIsraelIsrael

Applicants

NameAddressCountryNationality
VISIC TECHNOLOGIES LTD.7 Golda Meir 7403650 Ness ZionaIsraelIsrael

Documents

NameDate
202447090709-FORM 18 [23-11-2024(online)].pdf23/11/2024
202447090709-COMPLETE SPECIFICATION [21-11-2024(online)].pdf21/11/2024
202447090709-DECLARATION OF INVENTORSHIP (FORM 5) [21-11-2024(online)].pdf21/11/2024
202447090709-DRAWINGS [21-11-2024(online)].pdf21/11/2024
202447090709-FORM 1 [21-11-2024(online)].pdf21/11/2024
202447090709-NOTIFICATION OF INT. APPLN. NO. & FILING DATE (PCT-RO-105-PCT Pamphlet) [21-11-2024(online)].pdf21/11/2024
202447090709-PRIORITY DOCUMENTS [21-11-2024(online)].pdf21/11/2024
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