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REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IMPLEMENTING VEDIC MATH FOR LOW POWER CONSUMPTION
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Abstract
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REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IMPLEMENTING VEDIC MATH FOR LOW POWER CONSUMPTION
ORDINARY APPLICATION
Published
Filed on 27 June 2023
Patent Information
| Application ID | 202341043107 |
| Date of Application | 27/06/2023 |
Documents
| Name | Date |
|---|---|
| 202341043107-COMPLETE SPECIFICATION [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-DECLARATION OF INVENTORSHIP (FORM 5) [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-DRAWINGS [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-EDUCATIONAL INSTITUTION(S) [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-EVIDENCE FOR REGISTRATION UNDER SSI [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-EVIDENCE FOR REGISTRATION UNDER SSI(FORM-28) [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-FORM 1 [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-FORM FOR SMALL ENTITY(FORM-28) [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-FORM-9 [27-06-2023(online)].pdf | 27/06/2023 |
| 202341043107-REQUEST FOR EARLY PUBLICATION(FORM-9) [27-06-2023(online)].pdf | 27/06/2023 |
