POWER EFFICIENT STANDARD TERNARY INVERTER USING CNTFET

Abstract

The present invention relates to a power efficient standard ternary inverter using CNTFET with higher noise immunity. The power efficient standard ternary inverter comprises five CNTFETs labelled as “P1, P2, P3, N1, and N2,” with the chiral vector varied as (8,0), (10,0), and (19,0) to enhance the design. All STI designs are analyzed for various parameters using HSPICE simulator. The optimized STI reduces power consumption by 85%, increases speed by 80%, and achieves a 97% improvement in PDP. The optimized STI has a noise margin of 223 mV, which has been enhanced by 69%. Carbon nanotubes have emerged as a promising technology for the development of ternary logic circuits, which offer advantages over traditional binary logic in terms of power efficiency and information density. The unique electronic properties of CNTs, such as their high carrier mobility and ability to exhibit both metallic and semiconducting behavior, make them well-suited for ternary logic applications.

Specification

Description:Field of the Invention
The present invention relates to a power efficient standard ternary inverter using CNTFET, more particular to a power efficient standard ternary inverter using CNTFET with higher noise immunity.
Background of the Invention
The inherent advantages of ternary logic, such as reduced transistor count and improved power efficiency, make CNT-based ternary circuits suitable for a variety of embedded systems and data transmission applications. Researchers have found that ternary circuits based on CNTFETs work better than binary circuits in terms of power-delay product and transistor count. This is especially true when designing arithmetic logic units and other complex logic circuits. CNTFET technology offers significant advantages, including high driven current and reduced power consumption. One unique feature of CNTFETs is their ability to modify threshold voltage (Vth) by changing the diameter of CNT (DCNT). CNTs, a carbon allotrope discovered in 1991, have exceptional electrical, mechanical, and thermal characteristics, making them a top choice for enhanced performance in integrated circuits.
Ternary logic operates with three states as opposed to the two states of binary logic. This reduces the number of interconnects required in a circuit, simplifying the wiring and reducing signal congestion. The traditional design of ternary gates with a high transistor count elevates power consumption. Two transistors (p-type and n-type) in a ternary gate, always in a conductive state, constitute the voltage divider. The voltage divider method reduces the circuit's ON-current and power dissipation. Ternary designs like as inverters and universal gates utilize twin supply voltages and a minimal transistor count.
Traditional methods of designing ternary gates with a large transistor count result in higher power consumption. Recent ternary gate designs as standard ternary inverters and universal gates use dual supply voltages and fewer transistors. To optimize ternary circuits, some designs have replaced ternary with binary gates to further reduce transistor count and power consumption.
Drawings
Figure 1 (a) Representation of four noise margins (b) Overlapped VTCs of proposed STI
Figure 2. Proposed STI
Figure 3. Timing diagram of the proposed STI
Detailed Description of the Invention
The following description includes the preferred best mode of one embodiment of the present invention. It will be clear from this description of the invention that the invention is not limited to these illustrated embodiments but that the invention also includes a variety of modifications and embodiments thereto. Therefore, the present description should be seen as illustrative and not limiting. While the invention is susceptible to various modifications and alternative constructions, it should be understood, that there is no intention to limit the invention to the specific form disclosed, but, on the contrary, the invention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the invention as defined in the claims.
In any embodiment described herein, the open-ended terms "comprising," "comprises," and the like (which are synonymous with "including," "having" and "characterized by") may be replaced by the respective partially closed phrases "consisting essentially of," consists essentially of," and the like or the respective closed phrases "consisting of," "consists of, the like. As used herein, the singular forms "a", "an", and "the" designate both the singular and the plural, unless expressly stated to designate the singular only.
Four NMs, NM0, NM1-, NM1+, and NM2 are shown in figure 1(a), which is used to calculate the noise margin. The smallest of four-noise margins is considered as SNM. The overlay VTC of the optimised STI is illustrated in figure 1(b) to determine NM. The optimized STI has an NM of 223mV, which is 69% higher than conventional designs.

Figure 1 depicts the optimized STI design, incorporating five CNTFETs labelled as "P1, P2, P3, N1, and N2," with the chiral vector varied as (8,0), (10,0), and (19,0) to enhance the design. The DCNT is described by equation (1).
D_CNT=(a/p) v(n^2+m^2+nm)?0.079v(n^2+m^2+nm) (1)
Where, a ?0.249 nm. By taking m=0 into consideration, DCNT is entirely defined by the chiral vector n. Vth is evaluated by equation (2):
V_th=E_g/2e=v3/3× ?aV?_p/?eD?_CNT ˜0.43/(D_CNT (n,m)) (2)
Where, Vp =3.033 eV

The proposed STI circuit operation can understand by turning point of each transistor. When the input is low, P1 and P3 turn ON, while N1 and N2 turn OFF, and P2 turns OFF as well, resulting in an output of logic 2. When the input is high, P1, P3, and N2 turn OFF, while N1 turns ON, activating P2, and the output is logic 1. When the input reaches the high logic level, all P-CNTFETs turn OFF, and all N-CNTFETs turn ON, causing the output to settle at logic level 0 due to discharging.
Various parameters used to evaluate the efficiency of both the proposed and existing STI circuits are detailed in Table 1. All designs use three CNTs, with chirality ranging from (8,0) to (19,0). Figure 3 shows the timing diagram for the optimized STI design and verify the truth table. STI circuits from references [ M. H. Moaiyeri et al. (2019)] and [ M. Takbiri et al. (2019)] consume less power by stacking two transistors, though this increases delay due to the additional transistors. The STI circuits operate on either single or dual power supplies, as noted in Table 1. The proposed design outperforms others, using the same number of transistors as in [ R. A. Jaber et al. (2019)], by efficient transistor sizing. The proposed STI design reduces power consumption by 85%, increases speed by 80%, and improves PDP by 97%.
The overlapped voltage transfer characteristic (VTC) of the proposed STI circuit is depicted in Figure 1(b), which is used to determine the noise margin (NM). The NM value is based on the length of the longest side of the largest square that can be drawn in each of the four smaller sections. Four noise margins, labeled NM0, NM1-, NM1+, and NM2, are computed, and the minimum of these values is taken as the overall noise margin. The NM of the proposed STI circuit is 223 mV, representing increases of 69%, 32%, 30%, and 7% compared to existing circuit respectively.
Table 1. Performance evaluation of STIs
STI
Circuits Average Power (nW) Delay
(ps) PDP (aJ) No. of transistors Chirality Supply
count Noise margin (mV)
R. A. Jaber et al.
(2019) 38.649 13.953 0.5393 5 (10,0) (13,0) (19,0) 2 69
M. H. Moaiyeri et al.
(2019) 22.637 2.522 0.0571 6 (10,0) (13,0) (19,0) 1 156
M. Takbiri et al.
(2019) 9.660 5.695 0.0550 8 (8,0) (10,0) (19,0) 1 150
S. Etezadi et al.
(2019) 9.988 7.959 0.0795 10 (8,0) (19,0) 2 207
Proposed STI 5.822 2.777 0.0162 5 (8,0) (10,0) (19,0) 2 223


, Claims:1. A power efficient standard ternary inverter using CNTFET, comprises of five CNTFETs labelled as "P1, P2, P3, N1, and N2," with the chiral vector varied as (8,0), (10,0), and (19,0) to enhance the design.
2. The power efficient standard ternary inverter using CNTFET as claimed in the claim 1, wherein SIT circuit comprising:
a) A first p-channel transistor (P1), a second p-channel transistor (P2), and a third p-channel transistor (P3), and a first n-channel transistor (N1) and a second n-channel transistor (N2), all of which are CNTFETs (Carbon Nanotube Field Effect Transistors);
b) A logic input signal configured to control the state of said transistors, wherein:
i. When the input signal is at a low logic level:
• P1 and P3 are turned ON;
• N1 and N2 are turned OFF;
• P2 is turned OFF;
• The output of the circuit is logic level 2.
ii. When the input signal is at a high logic level:
• P1 and P3 are turned OFF;
• N1 is turned ON;
• P2 is turned ON;
• The output of the circuit is logic level 1.
iii. when the input signal reaches a high logic level and remains stable:
• All p-channel CNTFETs (P1, P2, P3) are turned OFF;
• All n-channel CNTFETs (N1, N2) are turned ON;
• The output of the circuit settles at logic level 0 due to discharging.
3. The power efficient standard ternary inverter using CNTFET as claimed in the claim 1, wherein optimized standard ternary inverter (STI) reduces power consumption by 85%, increases speed by 80%, and achieves a 97% improvement in PDP.
4. The power efficient standard ternary inverter using CNTFET as claimed in the claim 1, wherein optimized STI has a noise margin of 223 mV, which has been enhanced by 69%.

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