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PIPELINED RECONFIGURABLE HIGH SPEED MEMORY OPTIMIZED DISTRIBUTIVE ARITHMETIC (RHSDA) FOR 2D DTCWT AND INVERSE DTCWT ARCHITECTURE FOR LEVEL-1 AND HIGHER LEVEL IMAGE ANALYSIS AND SYNTHESIS
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Abstract
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PIPELINED RECONFIGURABLE HIGH SPEED MEMORY OPTIMIZED DISTRIBUTIVE ARITHMETIC (RHSDA) FOR 2D DTCWT AND INVERSE DTCWT ARCHITECTURE FOR LEVEL-1 AND HIGHER LEVEL IMAGE ANALYSIS AND SYNTHESIS
ORDINARY APPLICATION
Published
Filed on 5 February 2021
Patent Information
| Application ID | 202141004942 |
| Date of Application | 05/02/2021 |
Documents
| Name | Date |
|---|---|
| 202141004942-COMPLETE SPECIFICATION [05-02-2021(online)].pdf | 05/02/2021 |
| 202141004942-DECLARATION OF INVENTORSHIP (FORM 5) [05-02-2021(online)].pdf | 05/02/2021 |
| 202141004942-DRAWINGS [05-02-2021(online)].pdf | 05/02/2021 |
| 202141004942-FORM 1 [05-02-2021(online)].pdf | 05/02/2021 |
