PERFORMANCE ENHANCEMENT OF 6T AND 9T SRAM USING 90 NM TECHNOLOGY

Abstract

ABSTRACT The present invention provides 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability, as well as decreased leakage power when compared to 6T, 7T, and 8T.

Specification

Description:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Performance Enhancement of 6T And 9T SRAM Using 90 nm Technology




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.


Performance Enhancement of 6T And 9T SRAM Using 90 nm Technology

Field of Invention:
The present invention relates to providing new 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
SRAM is the conventional SRAM design. This is made up of six transistors, where two of the transistors are of PMOS which then replace the resistive load used in 4T design. The configuration is such that the PMOS and NMOS form a cross- coupled inverter while two NMOS transistors are connected one each to the bit lines.
Operation
During reading, the memory cell's WL activates. BL and BLBAR receive voltage. Active WL triggers access transistor, causing BL voltage drop for logic 1. Sense amplifiers detect voltage differences to determine stored data, latching output as Q and QBAR. RWL ensures that only designated cell is enabled.
B. Hold Operation
During the hold, BL and BLBAR maintain predetermined voltage levels. Turning off WL isolates the memory cell by deactivating its access transistor. RWL, when activated, strengthens cell isolation, ensuring only the chosen cell is in the hold state. Data remains static with disabled WL and possibly RWL. Q and QBAR outputs hold stored data. Collaborative efforts maintain data integrity, ensuring reliable storage until future read or write operations.
C. Write Operation
During write, isolation ensures neighboring cells remain unaffected. Precharge and activation of WL and RWL maintain data integrity. Writing a logical zero deactivates the NMOS access transistor, isolating the cell and preserving its state. Writing a logical one activates the access transistor, connecting storage nodes and bit lines, storing the value. The logical state persists in the cell.
The present invention provides a new 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability.

Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability.

Summary of the Invention:
In an embodiment, the present invention provides 9T SRAM and evaluates its performance against conventional 6T SRAM regarding stability and process variation. Utilizing a symmetrical design, the 9T SRAM employs a differential read operation for faster access times. Activation of RWL during reads turns on MN5 and MN6, enhancing pull-down strength and reducing resistance between storage nodes and ground, minimizing voltage rise at node Q. Write operations involve WL activation, RWL deactivation, and write enable signal insertion. MN5 and MN6 limit leakage during writes, while increasing their width to length ratio improves SNM, enhancing overall performance and stability.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates schematic of 6T SRAM.
Figure 2: illustrates schematic of 9T SRAM.
Figure 3: illustrates Transient analysis of 6T SRAM.
Figure 4: illustrates Transient analysis of 9T SRAM.
Figure 5: illustrates DC analysis of 6T SRAM.
Figure 6: illustrates DC analysis of 9T SRAM.
Figure 7: illustrates DC analysis of 6T SRAM with varying temperature.
Figure 8: illustrates DC analysis of 9T SRAM with varying temperature.
Figure 9: illustrates Q-point analysis of 6T SRAM.
Figure 10: illustrates Q-point analysis of 9T SRAM.
Figure 11: illustrates SNM curve of 6T SRAM.
Figure 12: illustrates SNM curve of 9T SRAM.
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides a new 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability, as well as decreased leakage power when compared to 6T, 7T, and 8T.
In the present invention, 6T and 9T SRAM cells to assess their stability and analyze their behavior. The 9T configuration presented in this study is a design paradigm for low-power and durable logic circuits under process variation that minimizes dynamic and static current (power) consumption in 9T SRAM bit cells.
OPERATIONS OF 6T SRAM
A. Read Operation
During reading, the memory cell's WL activates. BL and BLBAR receive voltage. Active WL triggers access transistor, causing BL voltage drop for logic 1. Sense amplifiers detect voltage differences to determine stored data, latching output as Q and QBAR. RWL ensures that only designated cell is enabled.
B. Hold Operation
During the hold, BL and BLBAR maintain predetermined voltage levels. Turning off WL isolates the memory cell by deactivating its access transistor. RWL, when activated, strengthens cell isolation, ensuring only the chosen cell is in the hold state. Data remains static with disabled WL and possibly RWL. Q and QBAR outputs hold stored data. Collaborative efforts maintain data integrity, ensuring reliable storage until future read or write operations.
C. Write Operation
During write, isolation ensures neighboring cells remain unaffected. Precharge and activation of WL and RWL maintain data integrity. Writing a logical zero deactivates the NMOS access transistor, isolating the cell and preserving its state. Writing a logical one activates the access transistor, connecting storage nodes and bit lines, storing the value. The logical state persists in the cell.
OPERATIONS OF 9T SRAM
A. Read Operation
During read, the memory cell's WL activates. BL and BLBAR receive voltage. Active WL triggers access transistor, causing BL voltage drop for logic 1. Sense amplifiers detect voltage difference to determine stored data, latching output as Q and QBAR. RWL ensures only designated cell is enabled.
B. Hold Operation
During hold, BL and BLBAR maintain predetermined voltage levels. Turning off WL isolates the memory cell by deactivating its access transistor. RWL, when activated, strengthens cell isolation, ensuring only the chosen cell is in hold state. Data remains static with disabled WL and possibly RWL. Q and QBAR outputs hold stored data. Collaborative efforts maintain data integrity, ensuring reliable storage until future read or write operations.
C. Write Operation
During write, isolation ensures neighboring cells remain unaffected. Precharge and activation of WL and RWL maintain data integrity. Writing a logical zero deactivates the NMOS access transistor, isolating the cell and preserving its state. Writing a logical one activates the access transistor, connecting storage nodes and bit lines, storing the value. The logical state persists in the cell.
V. TRANSIENT ANALYSIS OF 6T AND 9T SRAM

A. 6T SRAM
The timing diagram illustrates the write mode of a 6T SRAM cell using 1.8V and 90 nm CMOS technology [10]. It focuses on the transient response. BL and BLBAR represent input data. The wordline signal triggers write or hold operations: high for writing, low for holding previous data. Q and QB represent the written data in the cell, complementing each other. For instance, if Q stores '0', QB stores '1'.

B. 9T SRAM
Before any operations, set starting conditions for nodes: Q and QBAR, WL, RWL, BL, and BLBAR, reflecting prior status or surrounding circumstances. Activate WL to read or write data, connecting access transistor to bit lines for data transfer. Observe WL activation's impact on Q, QBAR, BL, and BLBAR voltages. Use RWL, if necessary, to isolate neighboring cells during WL activation. Monitor Q, QBAR, BL, and BLBAR voltage changes during RWL activation. Simulate read or write operations by providing proper signals to BL and BLBAR, monitoring voltage variations.

VI. DC ANALYSIS OF 6T AND 9T SRAM

A. 6T SRAM
In a 6T SRAM cell, six transistors form a cross-coupled configuration with two inverters, each comprising NMOS and PMOS pairs, and two access transistors for read/write. Q and QBAR are complementary outputs representing stored data. During DC analysis, static voltages are applied to analyze steady-state behavior. Q and QBAR maintain logic values when Vin is low (0V); access transistors are off. At Vin = 1.8V, access transistors conduct, potentially affecting inverters. Based on input data and cell state, Q and QBAR update logic values.

B. 9T SRAM
In a DC study, steady-state voltages of nodes in a 9T SRAM cell are analyzed during read, write, and hold procedures. The voltage range of 0 to 1.8 volts represents typical CMOS supply voltages. During reads, Q and QBAR stabilize to different voltages based on stored data and bit line voltages. Write operations alter Q and QBAR voltages to store new data. Q and QBAR remain stable during holds. Bit line precharge and stored data affect BL and BLBAR voltages during reads. Adjusting BL and BLBAR voltages writes new data. WL activates the chosen cell, while RWL isolates it during reads or writes for proper cell separation.

VII. DC ANALYSIS OF 6T AND 9T WITH VARYING TEMPERATURE

A. 6T SRAM
When analyzing the temperature impact on a 6T SRAM cell up to 60°C, consider Threshold Voltage Variation, affecting stability and read/write capabilities; Mobility Variation, potentially altering access time; Leakage Currents, impacting data stability and power consumption; Temperature Coefficients, explaining parameter variations. Understanding these factors is crucial for representing the SRAM cell's behavior across temperature ranges accurately.

B. 9T SRAM
DC analysis of a 9T SRAM cell at various temperatures, up to 60°C, is vital for assessing Q and QBAR node voltages. Utilize temperature-dependent models to accurately represent component behavior. Conduct analysis at intervals (e.g., every 20°C) within the range. Observing node voltages at each temperature enables optimization techniques to enhance stability and reliability against temperature variations. Higher temperatures may increase leakage currents, impacting data stability and power consumption. Understanding temperature coefficients for each transistor is crucial for depicting the SRAM cell's performance accurately across temperature ranges.
POINT ANALYSIS OF 6T AND 9T SRAM

A. 6T SRAM
In static random-access memory (SRAM), the Q point, or quiescent point, represents the transistor or circuit's operating point without a signal input [11], [12]. Determining biasing conditions, such as voltages and currents, for the transistors in a 6T SRAM cell during idle states is essential in DC analysis [13]. This includes assessing the behavior of pull-up (usually PMOS) and access (typically NMOS) transistors to ensure proper SRAM functionality during read/write operations and stability during idle periods [14]-[16].

B. 9T SRAM
In DC analysis of a 9T SRAM cell, the Q point, determined by steady-state voltages at Q and QBAR nodes during read, write, or hold operations, is crucial [17], [18]. Stimulate the SRAM cell appropriately, activating WL for reads/writes, and monitor Q and QBAR voltages. Ensure stability and functionality by verifying Q point against operational requirements, considering factors like supply voltage, temperature, and process variables. Analyze effects of various operational factors on the Q point, identifying any disturbances or issues.
IX. SNM CURVE OF 6T AND 9T SRAM

A. 6T SRAM
In a 6T SRAM cell, the voltage gap between read and write trip points is the static noise margin (SNM), vital for data stability. SNM is assessed by inducing read/write disturbances to determine state reversal voltage, indicating better noise immunity and stability. Reliable operation across environments and process variations is imperative. The SNM curve plots the stability margins of the SRAM cell against different voltage conditions applied to BL, BLBAR, Q, and QBAR. By varying these voltages and observing the stability of the stored data, one can construct the SNM curve.

B. 9T SRAM
Utilizing a symmetrical design, the 9T SRAM employs a differential read operation for faster access times. Activation of RWL during reads turns on MN5 and MN6, enhancing pull-down strength and reducing resistance between storage nodes and ground, minimizing voltage rise at node Q. Write operations involve WL activation, RWL deactivation, and write enable signal insertion. MN5 and MN6 limit leakage during writes, while increasing their width to length ratio improves SNM [19], [20], enhancing overall performance and stability.

X. CONCLUSION
The comparison research between the two shows that the new 9T SRAM has clear advantages over the conventional 6T SRAM. A comprehensive suite of tests, including as temperature fluctuations, DC and transient investigations, and Q-point evaluations, show that the 9T SRAM performs consistently better than its predecessor.During read, hold, and write operations, the 9T SRAM ensures great data stability due to its significantly enhanced Static Noise Margin (SNM). Its symmetrical architecture and differential read operation effectively eliminate process variations and voltage swings, increasing overall dependability. Furthermore, SNM is strengthened by larger transistors and RWL activation during reads and writes, which enhances noise resistance and ensures reliable memory operation. These findings support the 9T SRAM's status as an innovative technology that offers enhanced SNM along with appreciable increases in performance and reliability. Adopting novel ideas like the 9T SRAM could lead to previously undiscovered opportunities for memory efficiency and dependability, improving the prospects for semiconductor technology.
, Claims:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Performance Enhancement of 6T And 9T SRAM Using 90 nm Technology




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.


Performance Enhancement of 6T And 9T SRAM Using 90 nm Technology

Field of Invention:
The present invention relates to providing new 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
SRAM is the conventional SRAM design. This is made up of six transistors, where two of the transistors are of PMOS which then replace the resistive load used in 4T design. The configuration is such that the PMOS and NMOS form a cross- coupled inverter while two NMOS transistors are connected one each to the bit lines.
Operation
During reading, the memory cell's WL activates. BL and BLBAR receive voltage. Active WL triggers access transistor, causing BL voltage drop for logic 1. Sense amplifiers detect voltage differences to determine stored data, latching output as Q and QBAR. RWL ensures that only designated cell is enabled.
B. Hold Operation
During the hold, BL and BLBAR maintain predetermined voltage levels. Turning off WL isolates the memory cell by deactivating its access transistor. RWL, when activated, strengthens cell isolation, ensuring only the chosen cell is in the hold state. Data remains static with disabled WL and possibly RWL. Q and QBAR outputs hold stored data. Collaborative efforts maintain data integrity, ensuring reliable storage until future read or write operations.
C. Write Operation
During write, isolation ensures neighboring cells remain unaffected. Precharge and activation of WL and RWL maintain data integrity. Writing a logical zero deactivates the NMOS access transistor, isolating the cell and preserving its state. Writing a logical one activates the access transistor, connecting storage nodes and bit lines, storing the value. The logical state persists in the cell.
The present invention provides a new 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability.

Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability.

Summary of the Invention:
In an embodiment, the present invention provides 9T SRAM and evaluates its performance against conventional 6T SRAM regarding stability and process variation. Utilizing a symmetrical design, the 9T SRAM employs a differential read operation for faster access times. Activation of RWL during reads turns on MN5 and MN6, enhancing pull-down strength and reducing resistance between storage nodes and ground, minimizing voltage rise at node Q. Write operations involve WL activation, RWL deactivation, and write enable signal insertion. MN5 and MN6 limit leakage during writes, while increasing their width to length ratio improves SNM, enhancing overall performance and stability.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates schematic of 6T SRAM.
Figure 2: illustrates schematic of 9T SRAM.
Figure 3: illustrates Transient analysis of 6T SRAM.
Figure 4: illustrates Transient analysis of 9T SRAM.
Figure 5: illustrates DC analysis of 6T SRAM.
Figure 6: illustrates DC analysis of 9T SRAM.
Figure 7: illustrates DC analysis of 6T SRAM with varying temperature.
Figure 8: illustrates DC analysis of 9T SRAM with varying temperature.
Figure 9: illustrates Q-point analysis of 6T SRAM.
Figure 10: illustrates Q-point analysis of 9T SRAM.
Figure 11: illustrates SNM curve of 6T SRAM.
Figure 12: illustrates SNM curve of 9T SRAM.
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides a new 9T SRAM CMOS 90nm scaling technology node allows for total data isolation from the bit lines or memory cell, limiting sneak paths and offering higher data read and write stability, as well as decreased leakage power when compared to 6T, 7T, and 8T.
In the present invention, 6T and 9T SRAM cells to assess their stability and analyze their behavior. The 9T configuration presented in this study is a design paradigm for low-power and durable logic circuits under process variation that minimizes dynamic and static current (power) consumption in 9T SRAM bit cells.
OPERATIONS OF 6T SRAM
A. Read Operation
During reading, the memory cell's WL activates. BL and BLBAR receive voltage. Active WL triggers access transistor, causing BL voltage drop for logic 1. Sense amplifiers detect voltage differences to determine stored data, latching output as Q and QBAR. RWL ensures that only designated cell is enabled.
B. Hold Operation
During the hold, BL and BLBAR maintain predetermined voltage levels. Turning off WL isolates the memory cell by deactivating its access transistor. RWL, when activated, strengthens cell isolation, ensuring only the chosen cell is in the hold state. Data remains static with disabled WL and possibly RWL. Q and QBAR outputs hold stored data. Collaborative efforts maintain data integrity, ensuring reliable storage until future read or write operations.
C. Write Operation
During write, isolation ensures neighboring cells remain unaffected. Precharge and activation of WL and RWL maintain data integrity. Writing a logical zero deactivates the NMOS access transistor, isolating the cell and preserving its state. Writing a logical one activates the access transistor, connecting storage nodes and bit lines, storing the value. The logical state persists in the cell.
OPERATIONS OF 9T SRAM
A. Read Operation
During read, the memory cell's WL activates. BL and BLBAR receive voltage. Active WL triggers access transistor, causing BL voltage drop for logic 1. Sense amplifiers detect voltage difference to determine stored data, latching output as Q and QBAR. RWL ensures only designated cell is enabled.
B. Hold Operation
During hold, BL and BLBAR maintain predetermined voltage levels. Turning off WL isolates the memory cell by deactivating its access transistor. RWL, when activated, strengthens cell isolation, ensuring only the chosen cell is in hold state. Data remains static with disabled WL and possibly RWL. Q and QBAR outputs hold stored data. Collaborative efforts maintain data integrity, ensuring reliable storage until future read or write operations.
C. Write Operation
During write, isolation ensures neighboring cells remain unaffected. Precharge and activation of WL and RWL maintain data integrity. Writing a logical zero deactivates the NMOS access transistor, isolating the cell and preserving its state. Writing a logical one activates the access transistor, connecting storage nodes and bit lines, storing the value. The logical state persists in the cell.
V. TRANSIENT ANALYSIS OF 6T AND 9T SRAM

A. 6T SRAM
The timing diagram illustrates the write mode of a 6T SRAM cell using 1.8V and 90 nm CMOS technology [10]. It focuses on the transient response. BL and BLBAR represent input data. The wordline signal triggers write or hold operations: high for writing, low for holding previous data. Q and QB represent the written data in the cell, complementing each other. For instance, if Q stores '0', QB stores '1'.

B. 9T SRAM
Before any operations, set starting conditions for nodes: Q and QBAR, WL, RWL, BL, and BLBAR, reflecting prior status or surrounding circumstances. Activate WL to read or write data, connecting access transistor to bit lines for data transfer. Observe WL activation's impact on Q, QBAR, BL, and BLBAR voltages. Use RWL, if necessary, to isolate neighboring cells during WL activation. Monitor Q, QBAR, BL, and BLBAR voltage changes during RWL activation. Simulate read or write operations by providing proper signals to BL and BLBAR, monitoring voltage variations.

VI. DC ANALYSIS OF 6T AND 9T SRAM

A. 6T SRAM
In a 6T SRAM cell, six transistors form a cross-coupled configuration with two inverters, each comprising NMOS and PMOS pairs, and two access transistors for read/write. Q and QBAR are complementary outputs representing stored data. During DC analysis, static voltages are applied to analyze steady-state behavior. Q and QBAR maintain logic values when Vin is low (0V); access transistors are off. At Vin = 1.8V, access transistors conduct, potentially affecting inverters. Based on input data and cell state, Q and QBAR update logic values.

B. 9T SRAM
In a DC study, steady-state voltages of nodes in a 9T SRAM cell are analyzed during read, write, and hold procedures. The voltage range of 0 to 1.8 volts represents typical CMOS supply voltages. During reads, Q and QBAR stabilize to different voltages based on stored data and bit line voltages. Write operations alter Q and QBAR voltages to store new data. Q and QBAR remain stable during holds. Bit line precharge and stored data affect BL and BLBAR voltages during reads. Adjusting BL and BLBAR voltages writes new data. WL activates the chosen cell, while RWL isolates it during reads or writes for proper cell separation.

VII. DC ANALYSIS OF 6T AND 9T WITH VARYING TEMPERATURE

A. 6T SRAM
When analyzing the temperature impact on a 6T SRAM cell up to 60°C, consider Threshold Voltage Variation, affecting stability and read/write capabilities; Mobility Variation, potentially altering access time; Leakage Currents, impacting data stability and power consumption; Temperature Coefficients, explaining parameter variations. Understanding these factors is crucial for representing the SRAM cell's behavior across temperature ranges accurately.

B. 9T SRAM
DC analysis of a 9T SRAM cell at various temperatures, up to 60°C, is vital for assessing Q and QBAR node voltages. Utilize temperature-dependent models to accurately represent component behavior. Conduct analysis at intervals (e.g., every 20°C) within the range. Observing node voltages at each temperature enables optimization techniques to enhance stability and reliability against temperature variations. Higher temperatures may increase leakage currents, impacting data stability and power consumption. Understanding temperature coefficients for each transistor is crucial for depicting the SRAM cell's performance accurately across temperature ranges.
POINT ANALYSIS OF 6T AND 9T SRAM

A. 6T SRAM
In static random-access memory (SRAM), the Q point, or quiescent point, represents the transistor or circuit's operating point without a signal input [11], [12]. Determining biasing conditions, such as voltages and currents, for the transistors in a 6T SRAM cell during idle states is essential in DC analysis [13]. This includes assessing the behavior of pull-up (usually PMOS) and access (typically NMOS) transistors to ensure proper SRAM functionality during read/write operations and stability during idle periods [14]-[16].

B. 9T SRAM
In DC analysis of a 9T SRAM cell, the Q point, determined by steady-state voltages at Q and QBAR nodes during read, write, or hold operations, is crucial [17], [18]. Stimulate the SRAM cell appropriately, activating WL for reads/writes, and monitor Q and QBAR voltages. Ensure stability and functionality by verifying Q point against operational requirements, considering factors like supply voltage, temperature, and process variables. Analyze effects of various operational factors on the Q point, identifying any disturbances or issues.
IX. SNM CURVE OF 6T AND 9T SRAM

A. 6T SRAM
In a 6T SRAM cell, the voltage gap between read and write trip points is the static noise margin (SNM), vital for data stability. SNM is assessed by inducing read/write disturbances to determine state reversal voltage, indicating better noise immunity and stability. Reliable operation across environments and process variations is imperative. The SNM curve plots the stability margins of the SRAM cell against different voltage conditions applied to BL, BLBAR, Q, and QBAR. By varying these voltages and observing the stability of the stored data, one can construct the SNM curve.

B. 9T SRAM
Utilizing a symmetrical design, the 9T SRAM employs a differential read operation for faster access times. Activation of RWL during reads turns on MN5 and MN6, enhancing pull-down strength and reducing resistance between storage nodes and ground, minimizing voltage rise at node Q. Write operations involve WL activation, RWL deactivation, and write enable signal insertion. MN5 and MN6 limit leakage during writes, while increasing their width to length ratio improves SNM [19], [20], enhancing overall performance and stability.

X. CONCLUSION
The comparison research between the two shows that the new 9T SRAM has clear advantages over the conventional 6T SRAM. A comprehensive suite of tests, including as temperature fluctuations, DC and transient investigations, and Q-point evaluations, show that the 9T SRAM performs consistently better than its predecessor.During read, hold, and write operations, the 9T SRAM ensures great data stability due to its significantly enhanced Static Noise Margin (SNM). Its symmetrical architecture and differential read operation effectively eliminate process variations and voltage swings, increasing overall dependability. Furthermore, SNM is strengthened by larger transistors and RWL activation during reads and writes, which enhances noise resistance and ensures reliable memory operation. These findings support the 9T SRAM's status as an innovative technology that offers enhanced SNM along with appreciable increases in performance and reliability. Adopting novel ideas like the 9T SRAM could lead to previously undiscovered opportunities for memory efficiency and dependability, improving the prospects for semiconductor technology.

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