OPTIMIZING SPACER WIDTH IN N-TYPE LATERAL HETERO-STRUCTURE JUNCTIONLESS TFETS

Abstract

ABSTRACT The present invention provides a system and method to analyze how the spacer width affects the performance parameters of the semiconductor devices and to provide an analytical approach and framework to effectively Optimizing the Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs and enhancing the performance parameters of devices, including the transconductance (gm), drain current (Ids), ratio of on/off current (ION/IOFF), threshold voltage (VT), and parasitic capacitances (Cgs, Cgd, and Cgg).

Specification

Description:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs

Field of Invention:
The present invention relates in the field of electronics and more particularly investigates the effects of spacer width modification on the functional features of junctionless tunnel field-effect transistors (JLTFETs) to enhance the features.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The desire for smaller electronic devices is being driven by technological breakthroughs, and classic FETs, like MOSFETs, encounter substantial hurdles when scaling down to nanoscale dimensions. These difficulties-which include increased manufacturing complexity and unfavorable performance characteristics like short-channel effects-highlight the pressing need for creative transistor substitutes. When it comes to getting around the restrains of traditional FETs, TFETs (Tunnel Field-Effect Transistors) become known as the experimental alternative. Through the technique of band-to-band tunneling (BTBT), TFETs offer effective solutions for problems like as leakage current and ambipolar conduction. Furthermore, its compatibility with complementary metal-oxide-semiconductor (CMOS) production techniques is intact.
Nevertheless, despite their enormous potential, TFETs have a several number of downsides, which includes low on-state current and more challenging manufacturing. Researchers have developed a specialized TFET variation called the junction-less TFET (JLTFET) to directly address these challenges. Instead of using normal junctions of p-n doping, JLTFETs use uniform high doping concentration across the drain, channel, and source regions, which constructively reduces short-channel effects and breaks the limitations to enhance the performance.
In this study, we investigate how the width of the SIGe/GaAs semiconductor spacer affects the performance of JLTFETs. Our ultimate objective is to provide priceless insights into the optimization of TFET designs suited for upcoming electronic applications by investigating the effect of spacer width variation on JLTFET characteristics.

The present invention enhances the performance parameters of devices by effectively Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs.
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide analytical approach to Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs and enhances the performance parameters of devices, including the transconductance (gm), drain current (Ids), ratio of on/off current (ION/IOFF), threshold voltage (VT), and parasitic capacitances (Cgs, Cgd, and Cgg).

Summary of the Invention:
In an embodiment, the present invention provides a system and method to analyze how the spacer width affects the performance parameters of the semiconductor devices and to provide an analytical approach and framework to effectively Optimizing the Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs and enhancing the performance parameters of devices, including the transconductance (gm), drain current (Ids), ratio of on/off current (ION/IOFF), threshold voltage (VT), and parasitic capacitances (Cgs, Cgd, and Cgg).

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates JLTFET 2-Dimention Structure.
Figure 2: illustrates Ids ~ Vgs plot for different spacer widths (Ws).
Figure 3: illustrates Band Energy plot for different Spacer Widths (Ws).
Figure 4: illustrates Transconductance(gm) plot for different Spacer Widths (Ws).
Figure 5: illustrates Gate's reliance on drain capacitance (Cgd) on different spacer widths (Ws).
Figure 6: illustrates Gate capacitance to the source (Cgs) plot for different Spacer Widths (Ws).
Figure 7: illustrates Total gate-to-gate capacitance curve (Cgg) for different Spacer Widths (Ws).
Figure 8: illustrates Subthreshold swing (SS) and ION/IOFF ratio for different spacer widths (Ws).

Figure 9: illustrates Threshold voltage (VT) for different Spacer Widths (Ws).
Figure 10: illustrates fT for different Spacer Widths (Ws)
Figure 11: illustrates GBWP plot for different Spacer Widths (Ws)
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides a 2-dimensional structure of the disclosed SiGe/GaAs-JLTFET device is depicted in Fig. 1. This applies high band gap composition GaAs at the drain and channel area and low band gap composite SiGe at the source area via band gap engineering. HfO2 and SiO2 are employed at both gates in the same thickness to prevent leakage current. A 2 nm gap is made between the polar gate (PG) and control gate (CG) in order to isolate them. The 2-D structure of the JLTFET is displayed in the remaining figure 1. GaAs is at the channel and drain in this instance, while SiGe is at the source. To mitigate Leakage current through gates, HfO2 and SiO2 is used at both gates. We are varying the spacer width, which isolates the Polar Gate and Control gate. Table I displays the technical specifications.
TABLE I. DEVICE ARCHITECTURE PARAMETERS
SiGe/GaAs-JLTFET
Elements Size Dimensions
Source/Channel/Drain Length 20 nm
CG/PG Thickness 2 nm
HfO2/SiO2 Thickness 1 nm
Polar Gate Work Function 5.93 eV
Control Gate Work Function 4.5 eV
SiGe/GaAs Material Thickness 3 nm
Spacer Thickness 2 nm
Spacer Width 2/3/4 nm

SIMULATION LAYOUT AND DEVICE CONFIGURATION
The Silvaco TCAD simulator is the primary tool used to model the device that is being described. It is adopted to compensate for the various physical processes involved in the functioning of the device. To precisely represent the recombination tunneling amount, the simulator specifically makes use of the Band-to-Band Tunneling (BTBT) sample. This involves specifying the boundaries at the channel/drain interface and establishing a quantum tunneling zone at the source/channel interface to permit both forward as well as reverse tunneling. Moreover, the presence of trap-assisted tunneling in the OFF state makes this model active as well. Shockley-Read-Hall and Auger recombination samples are utilized in accurately representing the carrier recombination process.

The Wentzel-Kramers-Brillouin method is used to compute the tunneling probability quantitatively. Additionally, Hansch's quantum confinement model is used to improve the simulation's accuracy. Throughout the simulation process, all carrier transport equations are solved numerically by Gummel and Newton's technique, ensuring a thorough and accurate understanding of device behaviour. By adjusting the spacer width of the JLTFET, assessing the characteristics, and recording the outcomes for later comparison. and drawing a graph using the 2 nm, 3 nm, and 4 nm values from the graphs.
We have examined the behavior of the transfer characteristics in figure 2. Furthermore, we've observed that, when the spacer width is 2 nm, the drain Current (Ids) increases to its maximum at lower gate voltages than at other widths. The drain current peaks remarkably decreased as the spacer's width increased. When we compare the 4nm and 2 nm spacer, we practically see a double variance in the drain current peak. We found that the drain current is maximum at 2 nm spacer width and lowest at 4 nm. Consequently, while taking into account spacer widths of 4 nm, 3 nm, and 2 nm, the maximum current is delivered at 2 nm.

Figure 3 shows that when the spacer width increases, junctionless tunnel field-effect transistors (JLTFETs) exhibit a noticeable trend of a decreasing band gap.
The spacer zone's expansion results in an increase in the tunneling range across the source and drain electrodes, which is what causes these phenomena. The outcome is a reduction in the effective band gap when carriers encounter a stronger electric field across the expanded spacer. This reduction in band gap affects the likelihood that carriers will tunnel through the junctionless channel, which in turn affects subthreshold swing, on/off current ratio, and switching speed, among other device performance metrics. Understanding and controlling this relationship between spacer width and band gap is crucial for optimizing JLTFET designs for specific applications, particularly in low-power electronics where minimizing energy barriers for carrier transport is paramount.
Figure 4 displays the transconductance (gm) changing as the spacer width changes; mathematically, it is expressed in equation. Transconductance, which predicts a device's behavior at higher frequencies, is crucial for RF performance. A greater gm value is ideal for improved RF performance. The graph analysis shows that the device exhibits the highest gm at a spacer width of 2 nm. As a result, the graph indicates that the spacer width should be set at 2 nm for the best radio frequency performance. This knowledge guarantees improved performance at higher frequencies during the design and optimization of radio frequency equipment.

It is seen in figure 5 that the capacitance Cgd does not change until a specific gate voltage is reached. Wider spacer widths also result in higher capacitances; the 4 nm spacer has the highest capacitance value, while the 2 nm spacer has the lowest.
The capacitance Cgs is shown in figure 6, which shows that the 4 nm spacer width consistently displays the maximum capacitance value within a given gate voltage range.
Two different kinds of parasitic capacitances, Cgd and Cgs, are shown in figures 5 and 6, respectively. Figure 7 shows the total parasitic capacitance, or Cgg, which is computed as the product of Cgs and Cgd. The RF performance of a device is greatly affected by these parasitic capacitances; lower levels are preferable for best results.
After examination, it is shown that when the spacer width (Ws) is adjusted to 2 nm, the described device shows the lowest value of parasitic capacitance. According to this research, setting the device with a spacer width of 2 nm is advantageous for reducing parasitic capacitance and improving overall performance from the standpoint of RF performance.
Figure 8, shows the current on/off interaction (ION/IOFF) and subthreshold oscillation (SS) for spacer widths of 2 nm, 3 nm, and 4 nm. The SS component largely establishes the switching function of the device; Lower values indicate greater performance. The graph unambiguously shows that the device exhibits the lowest SS with a spacer width of 2 nm, showing good switching abilities with this width. The ION/IOFF interaction is an additional critical metric that suggests device performance by interacting with on-state current (ION) and off-state current (IOFF). To maximize device efficiency, a high ION/IOFF ratio is desirable, indicating high ION and low IOFF values. The results shown in figure 2 further validate the higher performance of this arrangement since the device achieves its maximum ION/IOFF ratio at a spacer width of 2 nm.
Figure 9, displays the threshold levels of the junctionless tunnel field-effect transistors (JLTFETs) for various spacer widths. Interestingly, there is an aberrant trend where the lowest threshold voltage is recorded at 3 nm spacer width. This is not in line with the expected trend, as both the 2nm and 4nm spacer widths exhibit increased threshold voltages. Further investigation into this anomaly may provide details regarding the underlying factors influencing the threshold voltage behavior of JLTFETs.
The fT of the described device for different values of spacer widths is examined in figure 10. Given that the frequency when a system's output or performance starts to decline is known as fT. This parameter should, therefore, be high for good radio frequency behavior. The expression in equation (2) represents the mathematical form of fT. The device gives the greatest fT at 2 nm spacer width in Figure 10.


In figure 11, the GBWP of the given device is investigated by varying the Spacer widths (Ws). It is the range of frequencies within which a device can function. It should, therefore, be higher for a wider range of functioning, and this maximum value is found at WS = 2nm. Equation (3) expresses GBWP in mathematical form.


In summary, the present invention provides a system and method to analyze the effects of spacer width on the performance properties of junctionless tunneling field impact transistors, or JLTFETs. The study found that key metrics like drain current, threshold voltage, transconductance, and parasitic capacitances are significantly impacted by varying spacer lengths. The best results are often seen with a spacer width of 2 nm. The 2 nm spacer width is notable among other metrics because of its consistent superiority. These measurements integrate frequency-related properties such as fT and GBWP as well as RF performance indicators such as subthreshold oscillation and on/off current interaction. These findings demonstrate the critical role that spacer width tuning plays in enhancing the overall performance and efficiency of JLTFETs, and they provide valuable insights for future device design and manufacturing processes.
, Claims:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs

Field of Invention:
The present invention relates in the field of electronics and more particularly investigates the effects of spacer width modification on the functional features of junctionless tunnel field-effect transistors (JLTFETs) to enhance the features.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The desire for smaller electronic devices is being driven by technological breakthroughs, and classic FETs, like MOSFETs, encounter substantial hurdles when scaling down to nanoscale dimensions. These difficulties-which include increased manufacturing complexity and unfavorable performance characteristics like short-channel effects-highlight the pressing need for creative transistor substitutes. When it comes to getting around the restrains of traditional FETs, TFETs (Tunnel Field-Effect Transistors) become known as the experimental alternative. Through the technique of band-to-band tunneling (BTBT), TFETs offer effective solutions for problems like as leakage current and ambipolar conduction. Furthermore, its compatibility with complementary metal-oxide-semiconductor (CMOS) production techniques is intact.
Nevertheless, despite their enormous potential, TFETs have a several number of downsides, which includes low on-state current and more challenging manufacturing. Researchers have developed a specialized TFET variation called the junction-less TFET (JLTFET) to directly address these challenges. Instead of using normal junctions of p-n doping, JLTFETs use uniform high doping concentration across the drain, channel, and source regions, which constructively reduces short-channel effects and breaks the limitations to enhance the performance.
In this study, we investigate how the width of the SIGe/GaAs semiconductor spacer affects the performance of JLTFETs. Our ultimate objective is to provide priceless insights into the optimization of TFET designs suited for upcoming electronic applications by investigating the effect of spacer width variation on JLTFET characteristics.

The present invention enhances the performance parameters of devices by effectively Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs.
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide analytical approach to Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs and enhances the performance parameters of devices, including the transconductance (gm), drain current (Ids), ratio of on/off current (ION/IOFF), threshold voltage (VT), and parasitic capacitances (Cgs, Cgd, and Cgg).

Summary of the Invention:
In an embodiment, the present invention provides a system and method to analyze how the spacer width affects the performance parameters of the semiconductor devices and to provide an analytical approach and framework to effectively Optimizing the Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs and enhancing the performance parameters of devices, including the transconductance (gm), drain current (Ids), ratio of on/off current (ION/IOFF), threshold voltage (VT), and parasitic capacitances (Cgs, Cgd, and Cgg).

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates JLTFET 2-Dimention Structure.
Figure 2: illustrates Ids ~ Vgs plot for different spacer widths (Ws).
Figure 3: illustrates Band Energy plot for different Spacer Widths (Ws).
Figure 4: illustrates Transconductance(gm) plot for different Spacer Widths (Ws).
Figure 5: illustrates Gate's reliance on drain capacitance (Cgd) on different spacer widths (Ws).
Figure 6: illustrates Gate capacitance to the source (Cgs) plot for different Spacer Widths (Ws).
Figure 7: illustrates Total gate-to-gate capacitance curve (Cgg) for different Spacer Widths (Ws).
Figure 8: illustrates Subthreshold swing (SS) and ION/IOFF ratio for different spacer widths (Ws).

Figure 9: illustrates Threshold voltage (VT) for different Spacer Widths (Ws).
Figure 10: illustrates fT for different Spacer Widths (Ws)
Figure 11: illustrates GBWP plot for different Spacer Widths (Ws)
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides a 2-dimensional structure of the disclosed SiGe/GaAs-JLTFET device is depicted in Fig. 1. This applies high band gap composition GaAs at the drain and channel area and low band gap composite SiGe at the source area via band gap engineering. HfO2 and SiO2 are employed at both gates in the same thickness to prevent leakage current. A 2 nm gap is made between the polar gate (PG) and control gate (CG) in order to isolate them. The 2-D structure of the JLTFET is displayed in the remaining figure 1. GaAs is at the channel and drain in this instance, while SiGe is at the source. To mitigate Leakage current through gates, HfO2 and SiO2 is used at both gates. We are varying the spacer width, which isolates the Polar Gate and Control gate. Table I displays the technical specifications.
TABLE I. DEVICE ARCHITECTURE PARAMETERS
SiGe/GaAs-JLTFET
Elements Size Dimensions
Source/Channel/Drain Length 20 nm
CG/PG Thickness 2 nm
HfO2/SiO2 Thickness 1 nm
Polar Gate Work Function 5.93 eV
Control Gate Work Function 4.5 eV
SiGe/GaAs Material Thickness 3 nm
Spacer Thickness 2 nm
Spacer Width 2/3/4 nm

SIMULATION LAYOUT AND DEVICE CONFIGURATION
The Silvaco TCAD simulator is the primary tool used to model the device that is being described. It is adopted to compensate for the various physical processes involved in the functioning of the device. To precisely represent the recombination tunneling amount, the simulator specifically makes use of the Band-to-Band Tunneling (BTBT) sample. This involves specifying the boundaries at the channel/drain interface and establishing a quantum tunneling zone at the source/channel interface to permit both forward as well as reverse tunneling. Moreover, the presence of trap-assisted tunneling in the OFF state makes this model active as well. Shockley-Read-Hall and Auger recombination samples are utilized in accurately representing the carrier recombination process.

The Wentzel-Kramers-Brillouin method is used to compute the tunneling probability quantitatively. Additionally, Hansch's quantum confinement model is used to improve the simulation's accuracy. Throughout the simulation process, all carrier transport equations are solved numerically by Gummel and Newton's technique, ensuring a thorough and accurate understanding of device behaviour. By adjusting the spacer width of the JLTFET, assessing the characteristics, and recording the outcomes for later comparison. and drawing a graph using the 2 nm, 3 nm, and 4 nm values from the graphs.
We have examined the behavior of the transfer characteristics in figure 2. Furthermore, we've observed that, when the spacer width is 2 nm, the drain Current (Ids) increases to its maximum at lower gate voltages than at other widths. The drain current peaks remarkably decreased as the spacer's width increased. When we compare the 4nm and 2 nm spacer, we practically see a double variance in the drain current peak. We found that the drain current is maximum at 2 nm spacer width and lowest at 4 nm. Consequently, while taking into account spacer widths of 4 nm, 3 nm, and 2 nm, the maximum current is delivered at 2 nm.

Figure 3 shows that when the spacer width increases, junctionless tunnel field-effect transistors (JLTFETs) exhibit a noticeable trend of a decreasing band gap.
The spacer zone's expansion results in an increase in the tunneling range across the source and drain electrodes, which is what causes these phenomena. The outcome is a reduction in the effective band gap when carriers encounter a stronger electric field across the expanded spacer. This reduction in band gap affects the likelihood that carriers will tunnel through the junctionless channel, which in turn affects subthreshold swing, on/off current ratio, and switching speed, among other device performance metrics. Understanding and controlling this relationship between spacer width and band gap is crucial for optimizing JLTFET designs for specific applications, particularly in low-power electronics where minimizing energy barriers for carrier transport is paramount.
Figure 4 displays the transconductance (gm) changing as the spacer width changes; mathematically, it is expressed in equation. Transconductance, which predicts a device's behavior at higher frequencies, is crucial for RF performance. A greater gm value is ideal for improved RF performance. The graph analysis shows that the device exhibits the highest gm at a spacer width of 2 nm. As a result, the graph indicates that the spacer width should be set at 2 nm for the best radio frequency performance. This knowledge guarantees improved performance at higher frequencies during the design and optimization of radio frequency equipment.

It is seen in figure 5 that the capacitance Cgd does not change until a specific gate voltage is reached. Wider spacer widths also result in higher capacitances; the 4 nm spacer has the highest capacitance value, while the 2 nm spacer has the lowest.
The capacitance Cgs is shown in figure 6, which shows that the 4 nm spacer width consistently displays the maximum capacitance value within a given gate voltage range.
Two different kinds of parasitic capacitances, Cgd and Cgs, are shown in figures 5 and 6, respectively. Figure 7 shows the total parasitic capacitance, or Cgg, which is computed as the product of Cgs and Cgd. The RF performance of a device is greatly affected by these parasitic capacitances; lower levels are preferable for best results.
After examination, it is shown that when the spacer width (Ws) is adjusted to 2 nm, the described device shows the lowest value of parasitic capacitance. According to this research, setting the device with a spacer width of 2 nm is advantageous for reducing parasitic capacitance and improving overall performance from the standpoint of RF performance.
Figure 8, shows the current on/off interaction (ION/IOFF) and subthreshold oscillation (SS) for spacer widths of 2 nm, 3 nm, and 4 nm. The SS component largely establishes the switching function of the device; Lower values indicate greater performance. The graph unambiguously shows that the device exhibits the lowest SS with a spacer width of 2 nm, showing good switching abilities with this width. The ION/IOFF interaction is an additional critical metric that suggests device performance by interacting with on-state current (ION) and off-state current (IOFF). To maximize device efficiency, a high ION/IOFF ratio is desirable, indicating high ION and low IOFF values. The results shown in figure 2 further validate the higher performance of this arrangement since the device achieves its maximum ION/IOFF ratio at a spacer width of 2 nm.
Figure 9, displays the threshold levels of the junctionless tunnel field-effect transistors (JLTFETs) for various spacer widths. Interestingly, there is an aberrant trend where the lowest threshold voltage is recorded at 3 nm spacer width. This is not in line with the expected trend, as both the 2nm and 4nm spacer widths exhibit increased threshold voltages. Further investigation into this anomaly may provide details regarding the underlying factors influencing the threshold voltage behavior of JLTFETs.
The fT of the described device for different values of spacer widths is examined in figure 10. Given that the frequency when a system's output or performance starts to decline is known as fT. This parameter should, therefore, be high for good radio frequency behavior. The expression in equation (2) represents the mathematical form of fT. The device gives the greatest fT at 2 nm spacer width in Figure 10.


In figure 11, the GBWP of the given device is investigated by varying the Spacer widths (Ws). It is the range of frequencies within which a device can function. It should, therefore, be higher for a wider range of functioning, and this maximum value is found at WS = 2nm. Equation (3) expresses GBWP in mathematical form.


In summary, the present invention provides a system and method to analyze the effects of spacer width on the performance properties of junctionless tunneling field impact transistors, or JLTFETs. The study found that key metrics like drain current, threshold voltage, transconductance, and parasitic capacitances are significantly impacted by varying spacer lengths. The best results are often seen with a spacer width of 2 nm. The 2 nm spacer width is notable among other metrics because of its consistent superiority. These measurements integrate frequency-related properties such as fT and GBWP as well as RF performance indicators such as subthreshold oscillation and on/off current interaction. These findings demonstrate the critical role that spacer width tuning plays in enhancing the overall performance and efficiency of JLTFETs, and they provide valuable insights for future device design and manufacturing processes.

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