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MINIMIZATION OF LEAKAGE CURRENTS AND REDUCTION OF AREA OF MOSFET STRUCTURE FOR CMOS TRANSISTOR CIRCUITS IN THE SEMICONDUCTOR INDUSTRY
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MINIMIZATION OF LEAKAGE CURRENTS AND REDUCTION OF AREA OF MOSFET STRUCTURE FOR CMOS TRANSISTOR CIRCUITS IN THE SEMICONDUCTOR INDUSTRY
ORDINARY APPLICATION
Published
Filed on 10 August 2023
Patent Information
| Application ID | 202331053801 |
| Date of Application | 10/08/2023 |
Documents
| Name | Date |
|---|---|
| 202331053801-COMPLETE SPECIFICATION [10-08-2023(online)].pdf | 10/08/2023 |
| 202331053801-DRAWINGS [10-08-2023(online)].pdf | 10/08/2023 |
| 202331053801-FIGURE OF ABSTRACT [10-08-2023(online)].pdf | 10/08/2023 |
| 202331053801-FORM 1 [10-08-2023(online)].pdf | 10/08/2023 |
| 202331053801-REQUEST FOR EARLY PUBLICATION(FORM-9) [10-08-2023(online)].pdf | 10/08/2023 |
