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LOW POWER DEBUG ARCHITECTURE FOR SYSTEM-ONCHIPS (SOCS) AND SYSTEMS

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LOW POWER DEBUG ARCHITECTURE FOR SYSTEM-ONCHIPS (SOCS) AND SYSTEMS

PCT NATIONAL PHASE APPLICATION

Published

date

Filed on 1 February 2017

Patent Information

Application ID201747003702
Date of Application01/02/2017

Documents

NameDate
201747003702-US(14)-HearingNotice-(HearingDate-19-02-2024).pdf29/01/2024
201747003702-CLAIMS [30-12-2020(online)].pdf30/12/2020
201747003702-FER_SER_REPLY [30-12-2020(online)].pdf30/12/2020
201747003702-OTHERS [30-12-2020(online)].pdf30/12/2020
201747003702-PETITION UNDER RULE 137 [30-12-2020(online)].pdf30/12/2020
201747003702-FORM 3 [29-12-2020(online)].pdf29/12/2020
201747003702-Information under section 8(2) [29-12-2020(online)].pdf29/12/2020
201747003702-FER.pdf07/07/2020
Correspondence By Agent_Proof Of Right_09-08-2017.pdf09/08/2017
201747003702-Proof of Right (MANDATORY) [07-08-2017(online)].pdf07/08/2017
Abstract_201747003702.jpg20/05/2017
Form 13 [06-03-2017(online)].pdf06/03/2017
Marked Copy [06-03-2017(online)].pdf06/03/2017
Correspondence By Agent_Power Of Attorney_17-02-2017.pdf17/02/2017
Form 26 [14-02-2017(online)].pdf14/02/2017
Form 3 [10-02-2017(online)].pdf10/02/2017
Form 18 [03-02-2017(online)].pdf03/02/2017
201747003702.pdf02/02/2017
Description(Complete) [01-02-2017(online)].pdf01/02/2017
Description(Complete) [01-02-2017(online)].pdf_65.pdf01/02/2017
Drawing [01-02-2017(online)].pdf01/02/2017
Form 5 [01-02-2017(online)].pdf01/02/2017
Priority Document [01-02-2017(online)].pdf01/02/2017
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