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LOW-K SIDE-WALL SPACER BASED INNER GATE ENGINEERED JUNCTIONLESS SILICON NANOTUBE FET
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LOW-K SIDE-WALL SPACER BASED INNER GATE ENGINEERED JUNCTIONLESS SILICON NANOTUBE FET
ORDINARY APPLICATION
Published
Filed on 5 August 2020
Patent Information
| Application ID | 202011033495 |
| Date of Application | 05/08/2020 |
Documents
| Name | Date |
|---|---|
| 202011033495-Form 1-050820.pdf | 18/10/2021 |
| 202011033495-Form 2-050820.pdf | 18/10/2021 |
| 202011033495-Form 3-050820-.pdf | 18/10/2021 |
| 202011033495-Form 5-050820.pdf | 18/10/2021 |
