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LAYOUT OPTIMIZATION OF SHIFT REGISTERS BY NP SEPARATE TECHNIQUE USING OPTIMAL TRANSISTOR AND BRUTE FORCE ALGORITHM
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LAYOUT OPTIMIZATION OF SHIFT REGISTERS BY NP SEPARATE TECHNIQUE USING OPTIMAL TRANSISTOR AND BRUTE FORCE ALGORITHM
ORDINARY APPLICATION
Published
Filed on 10 February 2023
Patent Information
| Application ID | 202341009176 |
| Date of Application | 10/02/2023 |
Documents
| Name | Date |
|---|---|
| 202341009176-FORM-26 [15-02-2023(online)].pdf | 15/02/2023 |
| 202341009176-COMPLETE SPECIFICATION [10-02-2023(online)].pdf | 10/02/2023 |
| 202341009176-FORM 1 [10-02-2023(online)].pdf | 10/02/2023 |
| 202341009176-FORM-9 [10-02-2023(online)].pdf | 10/02/2023 |
| 202341009176-REQUEST FOR EARLY PUBLICATION(FORM-9) [10-02-2023(online)].pdf | 10/02/2023 |
