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LAYOUT AREA REDUCTION IN FULL CUSTOM INTEGRATED CIRCUITS
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LAYOUT AREA REDUCTION IN FULL CUSTOM INTEGRATED CIRCUITS
ORDINARY APPLICATION
Published
Filed on 28 January 2021
Patent Information
| Application ID | 202141003746 |
| Date of Application | 28/01/2021 |
Documents
| Name | Date |
|---|---|
| 202141003746-FER.pdf | 02/02/2022 |
| 202141003746-Abstract_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Claims_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Correspondence_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Description Complete_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Drawing_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Form18_Examination Request_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Form1_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Form2 Title Page_Complete_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Form3_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Form5_As Filed_28-01-2021.pdf | 28/01/2021 |
| 202141003746-Form9_Early Publication_28-01-2021.pdf | 28/01/2021 |
