IMPACT OF GE MOLE FRACTION ON THE PERFORMANCE OF SI1-XGEX/INAS CHARGED PLASMA-BASED JLTFET

Abstract

ABSTRACT The present invention provides a lateral n-type junctionless TFET architecture which consistently doped with a concentration of 1x 1019 cm-3. In this device, the charge plasma concept is implemented and used the polar gate and control gate, two isolated gates, with the control gate having a smaller work function than the polar gate. The main objective of these gates is to transform n+- n+- n+ architecture that is heavily doped into the typical p+-i-n+ structure.

Specification

Description:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Impact of Ge Mole Fraction on the Performance of Si1-xGex/InAs Charged Plasma-Based JLTFET




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

Impact of Ge Mole Fraction on the Performance of Si1-xGex/InAs Charged Plasma-Based JLTFET

Field of Invention:
The present invention relates to system and method to access the impact of the Ge mole fraction (x) on the electrical performance of the Si1-xGex/InAs charged plasma-based junctionless TFET (JLTFET).

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The size of MOSFET device is actively scaled down as CMOS technology moves closer to the nanoscale range for future VLSI technology. Aggressive scaling is used to create extremely dense VLSI circuits with high speed and low power consumption. Leakage currents are heightened by reducing device dimensions, especially the oxide thickness below specific thresholds. The increased leakage currents in ultra-scaled VLSI circuits also increase power consumption. Due to the small subthreshold slope (SS), tunnel field effect transistors (TFETs) are one of the top contenders for ultra-low power applications in nanoelectronics. Such devices may be operated at a substantially low power supply voltage, which results in an extremely small OFF-state current and a minimal amount of power dissipation in extremely dense VLSI circuits.
Recently many researchers have done a depth study on junctionless tunnel field effect transistors (JLTFETs). This is primarily due to the fact that JLTFET subthreshold slope is substantially smaller than 60 mV/decade which is the threshold for MOSFETs at ambient temperature. JLTFET is a quantum mechanical device that operates on a band-to-band tunneling mechanism. Nowadays, hetero-material JLTFETs have received more attention due to their enhanced electrical performance and less variability than MOSFET. However, homo-JLTFET provides enhanced is in more trend due to its superior tunneling current compared to homo-JLTFET.
In order to improve device properties like low OFF-state current and higher ON-state current, III-V compound semiconductors are currently receiving much more attention than Si. In order to examine the impact of Ge mole composition, the present invention have used Si1-xGex/InAs as semiconducting material in the device.
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide a device made by hetero-material engineering by incorporating Si1-xGex with InAs, and then band gap engineering is combined with junctionless technology for TFETs.

Summary of the Invention:
In an embodiment, the device of the present invention has a lateral n-type junctionless TFET architecture which consistently doped with a concentration of 1x 1019 cm-3. In this device, the charge plasma concept is implemented and used the polar gate and control gate, two isolated gates, with the control gate having a smaller work function than the polar gate. The main objective of these gates is to transform n+- n+- n+ architecture that is heavily doped into the typical p+-i-n+ structure.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates Graphical outlook of Si1-xGex/InAs JLTFET the present invention.
Figure 2: illustrates band energy variation of Si1-xGex/InAs device with Ge mole fraction in (a) OFF-Sate (b) ON-Sate.
Figure 3: illustrates carrier concentration variation with Ge mole fraction in (a) OFF-state (b) ON-state.
Figure 4: illustrates illustration of IDS ~ VGS characteristics at several values of Ge mole composition.
Figure 5: illustrates comparison of the current ratio of the mentioned device at various values of Ge mole composition (x).
Figure 6: illustrates variation of the electric field with Ge mole composition (x).
Figure 7: illustrates variation of transconductance with Ge mole fraction (x).
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the device of the present invention has a lateral n-type junctionless TFET architecture which consistently doped with a concentration of 1x 1019 cm-3. In this device, the charge plasma concept is implemented and used the polar gate and control gate, two isolated gates, with the control gate having a smaller work function than the polar gate. The main objective of these gates is to transform n+- n+- n+ architecture that is heavily doped into the typical p+-i-n+ structure. Table I lists the device's structural parameters. The control gate's and the polar gate's respective work functions are 4.5 eV and 5.93 eV.

Si1-xGex/InAs JLTFET
Parameters Values Units
Source Length 20 nm
Channel Length 20 nm
Drain Length 20 nm
Spacer Width 2 nm
Dielectric Thickness 2 nm
Polar Gate Work Function 5.93 eV
Control Gate Work Function 4.5 eV
The thickness of the Semiconductor Body 3 nm


The length of the polar gate and control gate is 18 nm and 20 nm, respectively. The primary role of the polar gate is to induce p+ type structure from n+, whereas the role of the control gate is to induce intrinsic type material (i-type) from the n+ substrate. As a dielectric material, a combination of HfO2 and SiO2 is used at both gates, with 1 nm thickness and 60 nm length of each.
The SILVACO-ATLAS 2-D simulator is used to perform the simulation of the device. Non-local band-to-band tunneling model is utilized because TFET operates on the band-to-band tunneling via the tunneling barrier. At each and every mesh node of the simulated structure, the non-local models are unaffected by the electric field. It is based on both the device's band structure and the bands' spatial fluctuation. The Auger recombination model and band gap narrowing (BGN) are also used. A model of tunneling with trap assistance is also used to account for the impacts of traps. The SRH recombination model is utilized because there are more impurities in the channel region. Invoking the CVT model (Lombardi) and Fermi-Dirac statistics is also done. The temperature-dependent mobility, perpendicular and parallel electric field mobility, and mobility dependent on concentration are also included in the CVT model. Because the thickness of the body is 3 nm, the quantum confinement model proposed by Hansch is also applied.
The dependency of band energy on Ge mole composition for the OFF state of a discussed device is shown in Fig. 2(a). As previously mentioned, Si1-xGex serves as the source, and InAs serve as the channel and drain in a Si1-xGex/InAs JLTFET. Due to the utilization of InAs at the channel and drain sections, in the OFF state the device has a significantly wider excavating barrier thickness. From Fig. 2(a), it is clear that the device has a maximum band gap at Ge mole fraction x = 0.1; due to the large band gap at x = 0.1, only a small number of electrons can move through the barrier to reach the drain region. As a result, the tunneling barrier of the device only allows a small amount of leakage current to pass through.
As shown in Fig. 2(b), when gate biassing is used, the conduction band of Si1-xGex/InAs JLTFET shifts down while the valence band is moved upward as a result of the electric field created by the control gate at the source/channel (So/Ch) contact. The band gap at the So/Ch contact depends on the Ge mole composition (x); it decreases with the increment in Ge mole composition (x) due to this device experiencing a high ON-state current at a higher Ge mole fraction (x). On the other side, OFF-state current also increases with an increment in the Ge mole composition (x). So, to keep the ION/IOFF ratio high, Ge mole fraction x = 0.1 is a better choice.
Fig. 3(a) and (b) depict the electron-hole concentration at several values of Ge mole composition (x) in the OFF and ON states, respectively. In the OFF-state, the p+-i-n+ structure is developed (see Fig. 3(a)) from the n+-n+-n+ structure due to the use of the polar gate and control gate at the source and channel section, respectively. At x = 0.1, the device shows a maximum p+-i-n+ tendency in respect of other values. When gate biassing is applied, electron concentration increases (see Fig. 3(b)).

This increment in electron concentration induces local minima of the conduction band at the So/Ch contact, which is the cause of the reduction in the band gap between the valence band of the source and the conduction band of the channel. With this decrement in the band gap, more electrons acquired sufficient energy to tunnel across the junction, improving the ON-state current. At x = 0.5, the device shows slightly more electron concentration in comparison to x = 0.1 values. Still, after considering other performance parameters, the x = 0.1-mole fraction is more suitable for analyzing the device's behavior.
Fig. 4 depicts the IDS ~ VGS characteristics of the above-mentioned device at several values of Ge mole composition (x). From Fig. 4, it is clear that the ON-state current increases when we increase the Ge mole composition (x); the reason for increment in the ON-state current is the decrement in the band gap at the So/Ch contact due to the implementation of hetero-material. But on the other side increment in the mole fraction also increases the OFF-state current (see Fig. 4); at x = 0.1 device has a minimum OFF-state current, and at x = 0.9 device has a maximum value of OFF-state current.
Further, Fig. 5 compares the current ratio of the mentioned device at several values of Ge mole composition (x). From Fig. 5, it is seen that the current ratio decreases with the increment in the Ge mole composition. The device has a maximum current ratio (3.8 x 107) at Ge mole fraction x = 0.1 and a minimum current ratio (2.7 x 103) at x = 0.9.
This type of result is obtained due to the dominance of OFF-state current over ON-state current as Ge mole composition increases.
Fig. 6 represents the vertical electrical field (Ey) values at different Ge mole composition values. For better reliability of the device, the vertical electric field should be minimum; a very high vertical electric field can be a reason for leakage current through the gate. So for realiability point of view selection of Ge mole fraction x = 0.9 is a good choice, but at this value, other parmaters of the device degraded drastically, so keeping reliability on a light note, we have considered x = 0.1 as a Ge mole composition in the entire paper.
Fig. 7 depicts the dependency of transconductance on Ge mole composition (x). It is the crucial parameter evaluated by performing differentiation of drain current concerning the gate voltage. This parameter is used to decide the linearity of any device. So for a high level of linearity, this parameter should be high. From Fig. 7, it is perceived that the device has the highest transconductance value at x = 0.3 and the lowest value at x = 0.9. But at x = 0.3, the OFF-state current is high (see Fig. 4), so for the device's proper functioning, we will prefer transconductancenace at x = 0.1 value.
In the present invention, the system analyses the impact of Ge mole fraction on performance parameters of Si1-xGex/InAs JLTFET made from hetero material composite Si1-xGex and InAs. Si1-xGex is applied at the source, and InAs is used at the drain and channel section based on the band gap and gate dielectric engineering concept. The mentioned device provides the lowest OFF-state current and significant ON-state current at x = 0.1 Ge mole composition. Besides this, the other performance parameters of the Si1-xGex/InAs JLTFET, like band energy, electron-hole concentration, vertical electrical field (Ey), and transconductance, are also highly considerable at x = 0.1 Ge mole composition. Therefore, based on the above analysis, Si1-xGex/InAs JLTFETs with a Ge mole composition of x = 0.1 may be suitable candiadte for high-speed operations, low leakage circuits, and easier fabrication because they use hetero-junctionless technology.
, Claims:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Impact of Ge Mole Fraction on the Performance of Si1-xGex/InAs Charged Plasma-Based JLTFET




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

Impact of Ge Mole Fraction on the Performance of Si1-xGex/InAs Charged Plasma-Based JLTFET

Field of Invention:
The present invention relates to system and method to access the impact of the Ge mole fraction (x) on the electrical performance of the Si1-xGex/InAs charged plasma-based junctionless TFET (JLTFET).

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The size of MOSFET device is actively scaled down as CMOS technology moves closer to the nanoscale range for future VLSI technology. Aggressive scaling is used to create extremely dense VLSI circuits with high speed and low power consumption. Leakage currents are heightened by reducing device dimensions, especially the oxide thickness below specific thresholds. The increased leakage currents in ultra-scaled VLSI circuits also increase power consumption. Due to the small subthreshold slope (SS), tunnel field effect transistors (TFETs) are one of the top contenders for ultra-low power applications in nanoelectronics. Such devices may be operated at a substantially low power supply voltage, which results in an extremely small OFF-state current and a minimal amount of power dissipation in extremely dense VLSI circuits.
Recently many researchers have done a depth study on junctionless tunnel field effect transistors (JLTFETs). This is primarily due to the fact that JLTFET subthreshold slope is substantially smaller than 60 mV/decade which is the threshold for MOSFETs at ambient temperature. JLTFET is a quantum mechanical device that operates on a band-to-band tunneling mechanism. Nowadays, hetero-material JLTFETs have received more attention due to their enhanced electrical performance and less variability than MOSFET. However, homo-JLTFET provides enhanced is in more trend due to its superior tunneling current compared to homo-JLTFET.
In order to improve device properties like low OFF-state current and higher ON-state current, III-V compound semiconductors are currently receiving much more attention than Si. In order to examine the impact of Ge mole composition, the present invention have used Si1-xGex/InAs as semiconducting material in the device.
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide a device made by hetero-material engineering by incorporating Si1-xGex with InAs, and then band gap engineering is combined with junctionless technology for TFETs.

Summary of the Invention:
In an embodiment, the device of the present invention has a lateral n-type junctionless TFET architecture which consistently doped with a concentration of 1x 1019 cm-3. In this device, the charge plasma concept is implemented and used the polar gate and control gate, two isolated gates, with the control gate having a smaller work function than the polar gate. The main objective of these gates is to transform n+- n+- n+ architecture that is heavily doped into the typical p+-i-n+ structure.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates Graphical outlook of Si1-xGex/InAs JLTFET the present invention.
Figure 2: illustrates band energy variation of Si1-xGex/InAs device with Ge mole fraction in (a) OFF-Sate (b) ON-Sate.
Figure 3: illustrates carrier concentration variation with Ge mole fraction in (a) OFF-state (b) ON-state.
Figure 4: illustrates illustration of IDS ~ VGS characteristics at several values of Ge mole composition.
Figure 5: illustrates comparison of the current ratio of the mentioned device at various values of Ge mole composition (x).
Figure 6: illustrates variation of the electric field with Ge mole composition (x).
Figure 7: illustrates variation of transconductance with Ge mole fraction (x).
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the device of the present invention has a lateral n-type junctionless TFET architecture which consistently doped with a concentration of 1x 1019 cm-3. In this device, the charge plasma concept is implemented and used the polar gate and control gate, two isolated gates, with the control gate having a smaller work function than the polar gate. The main objective of these gates is to transform n+- n+- n+ architecture that is heavily doped into the typical p+-i-n+ structure. Table I lists the device's structural parameters. The control gate's and the polar gate's respective work functions are 4.5 eV and 5.93 eV.

Si1-xGex/InAs JLTFET
Parameters Values Units
Source Length 20 nm
Channel Length 20 nm
Drain Length 20 nm
Spacer Width 2 nm
Dielectric Thickness 2 nm
Polar Gate Work Function 5.93 eV
Control Gate Work Function 4.5 eV
The thickness of the Semiconductor Body 3 nm


The length of the polar gate and control gate is 18 nm and 20 nm, respectively. The primary role of the polar gate is to induce p+ type structure from n+, whereas the role of the control gate is to induce intrinsic type material (i-type) from the n+ substrate. As a dielectric material, a combination of HfO2 and SiO2 is used at both gates, with 1 nm thickness and 60 nm length of each.
The SILVACO-ATLAS 2-D simulator is used to perform the simulation of the device. Non-local band-to-band tunneling model is utilized because TFET operates on the band-to-band tunneling via the tunneling barrier. At each and every mesh node of the simulated structure, the non-local models are unaffected by the electric field. It is based on both the device's band structure and the bands' spatial fluctuation. The Auger recombination model and band gap narrowing (BGN) are also used. A model of tunneling with trap assistance is also used to account for the impacts of traps. The SRH recombination model is utilized because there are more impurities in the channel region. Invoking the CVT model (Lombardi) and Fermi-Dirac statistics is also done. The temperature-dependent mobility, perpendicular and parallel electric field mobility, and mobility dependent on concentration are also included in the CVT model. Because the thickness of the body is 3 nm, the quantum confinement model proposed by Hansch is also applied.
The dependency of band energy on Ge mole composition for the OFF state of a discussed device is shown in Fig. 2(a). As previously mentioned, Si1-xGex serves as the source, and InAs serve as the channel and drain in a Si1-xGex/InAs JLTFET. Due to the utilization of InAs at the channel and drain sections, in the OFF state the device has a significantly wider excavating barrier thickness. From Fig. 2(a), it is clear that the device has a maximum band gap at Ge mole fraction x = 0.1; due to the large band gap at x = 0.1, only a small number of electrons can move through the barrier to reach the drain region. As a result, the tunneling barrier of the device only allows a small amount of leakage current to pass through.
As shown in Fig. 2(b), when gate biassing is used, the conduction band of Si1-xGex/InAs JLTFET shifts down while the valence band is moved upward as a result of the electric field created by the control gate at the source/channel (So/Ch) contact. The band gap at the So/Ch contact depends on the Ge mole composition (x); it decreases with the increment in Ge mole composition (x) due to this device experiencing a high ON-state current at a higher Ge mole fraction (x). On the other side, OFF-state current also increases with an increment in the Ge mole composition (x). So, to keep the ION/IOFF ratio high, Ge mole fraction x = 0.1 is a better choice.
Fig. 3(a) and (b) depict the electron-hole concentration at several values of Ge mole composition (x) in the OFF and ON states, respectively. In the OFF-state, the p+-i-n+ structure is developed (see Fig. 3(a)) from the n+-n+-n+ structure due to the use of the polar gate and control gate at the source and channel section, respectively. At x = 0.1, the device shows a maximum p+-i-n+ tendency in respect of other values. When gate biassing is applied, electron concentration increases (see Fig. 3(b)).

This increment in electron concentration induces local minima of the conduction band at the So/Ch contact, which is the cause of the reduction in the band gap between the valence band of the source and the conduction band of the channel. With this decrement in the band gap, more electrons acquired sufficient energy to tunnel across the junction, improving the ON-state current. At x = 0.5, the device shows slightly more electron concentration in comparison to x = 0.1 values. Still, after considering other performance parameters, the x = 0.1-mole fraction is more suitable for analyzing the device's behavior.
Fig. 4 depicts the IDS ~ VGS characteristics of the above-mentioned device at several values of Ge mole composition (x). From Fig. 4, it is clear that the ON-state current increases when we increase the Ge mole composition (x); the reason for increment in the ON-state current is the decrement in the band gap at the So/Ch contact due to the implementation of hetero-material. But on the other side increment in the mole fraction also increases the OFF-state current (see Fig. 4); at x = 0.1 device has a minimum OFF-state current, and at x = 0.9 device has a maximum value of OFF-state current.
Further, Fig. 5 compares the current ratio of the mentioned device at several values of Ge mole composition (x). From Fig. 5, it is seen that the current ratio decreases with the increment in the Ge mole composition. The device has a maximum current ratio (3.8 x 107) at Ge mole fraction x = 0.1 and a minimum current ratio (2.7 x 103) at x = 0.9.
This type of result is obtained due to the dominance of OFF-state current over ON-state current as Ge mole composition increases.
Fig. 6 represents the vertical electrical field (Ey) values at different Ge mole composition values. For better reliability of the device, the vertical electric field should be minimum; a very high vertical electric field can be a reason for leakage current through the gate. So for realiability point of view selection of Ge mole fraction x = 0.9 is a good choice, but at this value, other parmaters of the device degraded drastically, so keeping reliability on a light note, we have considered x = 0.1 as a Ge mole composition in the entire paper.
Fig. 7 depicts the dependency of transconductance on Ge mole composition (x). It is the crucial parameter evaluated by performing differentiation of drain current concerning the gate voltage. This parameter is used to decide the linearity of any device. So for a high level of linearity, this parameter should be high. From Fig. 7, it is perceived that the device has the highest transconductance value at x = 0.3 and the lowest value at x = 0.9. But at x = 0.3, the OFF-state current is high (see Fig. 4), so for the device's proper functioning, we will prefer transconductancenace at x = 0.1 value.
In the present invention, the system analyses the impact of Ge mole fraction on performance parameters of Si1-xGex/InAs JLTFET made from hetero material composite Si1-xGex and InAs. Si1-xGex is applied at the source, and InAs is used at the drain and channel section based on the band gap and gate dielectric engineering concept. The mentioned device provides the lowest OFF-state current and significant ON-state current at x = 0.1 Ge mole composition. Besides this, the other performance parameters of the Si1-xGex/InAs JLTFET, like band energy, electron-hole concentration, vertical electrical field (Ey), and transconductance, are also highly considerable at x = 0.1 Ge mole composition. Therefore, based on the above analysis, Si1-xGex/InAs JLTFETs with a Ge mole composition of x = 0.1 may be suitable candiadte for high-speed operations, low leakage circuits, and easier fabrication because they use hetero-junctionless technology.

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