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I2C BUS ARCHITECTURE USING SHARED CLOCK AND DEDICATED DATA LINES
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Abstract
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I2C BUS ARCHITECTURE USING SHARED CLOCK AND DEDICATED DATA LINES
PCT NATIONAL PHASE APPLICATION
Published
Filed on 20 September 2023
Patent Information
| Application ID | 202347063239 |
| Date of Application | 20/09/2023 |
Documents
| Name | Date |
|---|---|
| 202347063239-COMPLETE SPECIFICATION [20-09-2023(online)].pdf | 20/09/2023 |
| 202347063239-DECLARATION OF INVENTORSHIP (FORM 5) [20-09-2023(online)].pdf | 20/09/2023 |
| 202347063239-DRAWINGS [20-09-2023(online)].pdf | 20/09/2023 |
| 202347063239-FORM 1 [20-09-2023(online)].pdf | 20/09/2023 |
| 202347063239-POWER OF AUTHORITY [20-09-2023(online)].pdf | 20/09/2023 |
| 202347063239-PRIORITY DOCUMENTS [20-09-2023(online)].pdf | 20/09/2023 |
| 202347063239-STATEMENT OF UNDERTAKING (FORM 3) [20-09-2023(online)].pdf | 20/09/2023 |
