HIGH PERFORMANCE CONTINUOUS TIME DELTA SIGMA ADC FOR BIOMEDICAL APPLICATIONS

Abstract

This paper presents the design of a novel second-order, 14-bit resolution sigma-delta modulator, optimized for low-power biomedical applications. The modulator operates in the sub-threshold region and is implemented using 0.18μm TSMC CMOS technology, achieving a remarkable power consumption of only 800nW. By employing the coefficients of a second-order modulator, the design attains a saturation value of approximately 5-DBFS, ensuring high performance. To mitigate flicker noise, the modulator utilizes the Charge Domain Sampling (CDS) technique, further enhancing its noise immunity. The system is characterized by a Nyquist-rate sampling frequency of 100Hz, an oversampling frequency of 12.8kHz, and a maximum Signal-to-Noise-and-Distortion Ratio (SNDR) of 86dB. This innovative structure not only optimizes bandwidth and oversampling frequency but also improves the time resolution of the sigma-delta modulator, positioning it as an efficient and highly effective solution for biomedical sensing and data acquisition applications.

Specification

Description:FIELD OF INVENTION
The invention lies in the field of high-performance continuous-time delta-sigma analog-to-digital converters (ADCs), tailored for biomedical applications. It emphasizes ultra-low power consumption, high resolution, and noise resilience, making it ideal for wearable and implantable medical devices. This innovation addresses the critical demand for accurate physiological signal acquisition in modern healthcare diagnostics and monitoring systems.
BACKGROUND OF INVENTION
The growing demand for advanced biomedical devices has highlighted the need for high-performance analog-to-digital converters (ADCs) capable of accurately capturing physiological signals. Biomedical applications, such as electrocardiography (ECG), electroencephalography (EEG), and implantable monitoring devices, require ADCs with high resolution, low power consumption, and exceptional noise immunity to ensure precise signal acquisition from the human body. Traditional ADC architectures often fall short in meeting these stringent requirements, particularly in continuous-time operations where noise, power efficiency, and dynamic range are critical.
The continuous-time delta-sigma ADC has emerged as a preferred solution for such applications due to its inherent advantages in achieving high resolution and power efficiency. By utilizing oversampling and noise-shaping techniques, it offers superior performance in low-frequency, high-precision signal processing scenarios typical of biomedical systems. However, existing delta-sigma ADC designs face challenges such as increased distortion, thermal noise, and limited dynamic range in compact and portable form factors.
This invention addresses these challenges by introducing a high-performance continuous-time delta-sigma ADC specifically optimized for biomedical applications. It incorporates innovative design techniques to minimize noise, enhance resolution, and achieve ultra-low power consumption, making it particularly suitable for battery-operated and implantable devices. The architecture ensures robust performance even in noisy environments, enabling accurate detection of minute physiological signals. This advancement not only improves the efficiency and reliability of biomedical diagnostics but also paves the way for more compact and sophisticated medical devices, significantly advancing modern healthcare technology.
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SUMMARY
The invention presents a groundbreaking high-performance continuous-time delta-sigma analog-to-digital converter (ADC), meticulously engineered for the unique demands of biomedical applications. This ADC is a paradigm shift in medical signal acquisition, offering an unparalleled blend of high resolution, ultra-low power consumption, and exceptional noise resilience, essential for modern healthcare devices like electrocardiography (ECG), electroencephalography (EEG), and implantable medical systems.
At its core, the invention leverages continuous-time delta-sigma modulation technology, renowned for its ability to achieve high precision in low-frequency signal domains. Through innovative design enhancements, the ADC significantly mitigates thermal noise, distortion, and power inefficiencies, overcoming the traditional limitations of existing architectures. This enables the detection of even the most subtle physiological signals with remarkable accuracy, ensuring reliable monitoring and diagnostics.
A standout feature of the ADC is its adaptive noise-shaping capability, which dynamically optimizes signal fidelity under varying operational conditions. Its ultra-low power consumption ensures compatibility with battery-operated and implantable devices, extending device longevity and patient comfort. The design also incorporates advanced process calibration techniques to maintain robustness across diverse environmental and operational parameters, enhancing device reliability in real-world scenarios.
This invention not only meets but surpasses the stringent requirements of biomedical systems, enabling the development of compact, portable, and intelligent medical devices. It represents a critical leap forward in healthcare technology, empowering clinicians with precise and reliable tools for patient care while laying the foundation for future innovations in medical diagnostics and monitoring systems.
DETAILED DESCRIPTION OF INVENTION
Time-to-digital converters (TDCs) and analog-to-digital converters (ADCs) have become fundamental components in the design of digital signal processing circuits, driven by advancements in CMOS integrated circuit (IC) technology for efficient signal digitization. In the context of portable and implantable medical devices, ADCs play a crucial role in accurately capturing biomedical signals, such as electrocardiograms (ECG) and electroencephalograms (EEG). To meet the stringent power consumption requirements of these devices, ADCs must be optimized for low power while maintaining reliability. ADCs are generally classified into two categories: Nyquist-rate and oversampling ADCs. Nyquist-rate converters sample the input signal at the Nyquist rate, utilizing architectures such as pipeline, flash, folded, interpolating, and successive approximation (SAR). These are typically used in high-speed, lower-accuracy applications, but achieving high precision with these converters is challenging due to the non-ideal characteristics of analog circuits. In contrast, oversampling ADCs sample at a multiple of the Nyquist rate and employ quantization noise shaping techniques, enabling higher precision. Due to their robustness against non-ideal parameters, oversampling converters, such as sigma-delta converters, offer superior accuracy. A sigma-delta converter consists of two key components: an analog sigma-delta modulator and digitally implemented decimation filters. This paper presents a novel second-order delta-sigma modulator with 14-bit resolution and a power consumption of just 800nW. The proposed modulator enhances bandwidth frequency, oversampling frequency, and resolution to 50 Hz, 12.8 kHz, and 14 bits, respectively, all implemented using 0.18 µm TSMC CMOS technology with a supply voltage of 1 V.
System-Level Design
This section explores the system-level design of the proposed structure, which includes both the modulator design and an appropriate gain amplifier.
Modulator Design
Delta-Sigma Modulators (DSMs) are well-suited for analog-to-digital conversion systems, classified as oversampling ADCs, and are renowned for their ability to perform quantization noise shaping. By employing oversampling and noise shaping techniques, DSMs achieve a significantly improved signal-to-noise ratio (SNR). The conventional block diagram of a second-order sigma-delta modulator, designed for biomedical applications, is presented. Based on the coefficients of this system, the modulator provides an impressive SNDR of 81 dB, making it highly effective for biomedical use. Key specifications of a conventional ADC suitable for these applications are summarized.
To enhance performance, the SCHREIER toolbox functions are utilized to optimize the system's coefficients. After simulation with the optimized coefficients, the maximum SNDR improves to 86 dB. However, this optimization introduces challenges in circuit-level implementation, particularly due to the disparity between the inputs of the integrators. Achieving the necessary capacitor values becomes difficult, as it requires a capacitance ten times larger than others, complicating the design process. As a result, the modified system's block diagram is presented, addressing these implementation issues.

Figure 1: The conventional second order modulator
The key characteristics of a conventional ADC for medical applications are as follows:
• Input Voltage Range: 2 V differential
• Resolution: 10 bits
• Supply Voltage: 1.2 V
• Power Consumption: Less than 200 nW
• Nyquist Frequency: 50 Hz

Figure 2: The optimized second order modulator.

Figure 3: The modified second order modulator.
As shown, by adjusting specific parameters, such as eliminating the feed-forward path and optimizing the coefficients, the system can achieve an SNDR of approximately 86 dB. The dynamic range (DR) of the sigma-delta (SD) modulator is determined by the ratio of input signal power to noise power, expressed as:

where Psig represents the input signal power, while Pthermal and Pflicker correspond to the thermal and flicker noise powers of the proposed modulator. The dynamic range curve for the optimized structure illustrates this relationship. A circuit-level implementation of this enhanced system is discussed in the subsequent sections.
Amplifier Gain
When the amplifier gain exceeds a certain threshold, the modulator operates optimally. Simulations conducted in MATLAB reveal that the minimum required amplifier gain is 25 dB.
Noise Analysis Using CDS Technique
Flicker noise, a type of colored noise with high amplitude at low frequencies, is mitigated using the Correlated Dual Sampling (CDS) technique. In Phase 1, the flicker noise voltage is captured in the CDS, and in Phase 2, this noise is added to the input signal, effectively removing the flicker noise. Thermal noise is primarily determined by the internal capacitors, which have excellent approximation properties. The differential thermal noise is given by:

where k is the Boltzmann constant, T is the temperature, and C is the capacitance. Thermal noise significantly impacts the first stage of the modulator, limiting the circuit's sensitivity. This noise is transmitted to the output as a signal, but in the second stage, it is spectrally shaped by the second-order noise-shaping function, which reduces its effect on the output. In the proposed modulator, thermal noise is equivalent to quantization noise. Given a -5 dBFS input signal and an SNDR of 83 dB, the modulator's output power is calculated as:

where Psig and Pn are the output signal and noise powers, respectively. Consequently, the SNR is 83 dB. The value of the sampling capacitor CS1 is determined to be 5.33 pF, with the internal capacitor value calculated based on the oversampling rate. This relationship is further detailed in the subsequent analysis.
The dynamic range curve for the optimized structure and the simulated SNDR as a function of amplifier gain are presented, confirming the effectiveness of the design.

Figure 4: The dynamic range curve of the optimized structure.

Figure 5: The graph of simulated SNDR according to the amplifier gain.

Figure 6: (a) An equivalent switching circuit for removing the flicker noise and (b) equivalent circuit in ø2.
The oversampling rate (OSR) is given by the equation:

where fsf is the sampling frequency and fsig is the signal frequency. From this formula, the oversampling rate (OSR) is calculated to be 128. Based on the obtained OSR, the required value for the sampling capacitor is determined to be 41.6 f, which is similar to the parasitic capacitances. Therefore, a value of 200 f is selected for the sampling capacitor to accommodate these effects.
Circuit-Level Design of the Modulator
This section details the circuit parameters and design for the proposed modulator.
Switch Capacitor Circuit Design
The structure of the switch capacitor circuit is depicted in the diagram. The clock frequency is set to 12.8 kHz, which is double the oversampling rate of the signal. As shown, the circuit operates in two phases, ø1 and ø2. In phase ø1, the input signal is sampled, and in phase ø2, the signal is integrated.
Using the capacitor value calculated from the earlier equation and the system's coefficients, the value of the integrating capacitor Ci1 is determined as:

Table: Integrating Capacitors in the Proposed Switch Capacitor Structure

This table presents the values of the integrating capacitors optimized for the proposed switch capacitor circuit structure.

Figure 7: The proposed switch capacitor structure.
Switch Capacitor Circuit Design
The proposed modulator employs a single-stage amplifier, which eliminates the need for compensation due to its reliance on the load capacitor. The gain-bandwidth product (GBW) for a single-stage amplifier with transconductance (gm) and load capacitance (CL) is expressed as:

For this amplifier, a minimum transconductance of 400 nanosiemens is sufficient to meet the required unit gain-bandwidth (UGBW). A folded-cascode amplifier, as depicted in the design, is utilized for the circuit.
The biasing circuit of the amplifier includes a series of transistors that generate the necessary bias voltage for the amplifier operation. A common-mode feedback (CMFB) circuit, specifically tailored for the switch capacitor design, is presented. This CMFB circuit operates in the sub-threshold region, which allows it to drive currents at the nanoampere scale, significantly reducing power consumption.
Comparators play a crucial role in multi-stage delta-sigma (MDS) structures, contributing to reduced power consumption and enhanced speed. The design incorporates a comparator circuit commonly used in the second stage of an integrator. Additionally, a D-Flip Flop (DFF) is utilized to maintain the state and ensure accurate results.
The proposed circuit operates in the sub-threshold region and is implemented using 0.18 µm TSMC CMOS technology. Its layout prototype, with an active area of 525 μm×210  is shown below.

Figure 8: The layout prototype of the proposed circuit.
Post-layout simulations were performed, and the proposed modulator was analyzed across different CMOS technology corners. The output waveforms for these simulations are presented for various conditions.
Key Simulation Details:
• Sampling Frequency: 12.8 kHz
• Input Signal: A sinusoidal signal with a frequency of 12.5 Hz and an amplitude of 500 mV
• Optimization: The SCHREIER toolbox was used to optimize system coefficients.
The output spectrum of the modulator in various conditions, such as SS@85°C, TT@27°C, and FF@-40°C, is presented accordingly.
The simulations were conducted using Hspice software, with the resulting output data transferred to MATLAB for further analysis. For spectral analysis, a Hann-window function was applied to enhance the Fast Fourier Transform (FFT) capabilities, improving spectral sensitivity. The dynamic range of the post-layout simulated modulator versus SNR (dB) is demonstrated, achieving a dynamic range of 86 dB.
Monte Carlo simulations were also conducted to assess the comparator offset mismatch, as illustrated (with 500 runs and σ=4.2 mV).
Performance Summary:
• Power Consumption: 800 nW
• Figure of Merit (FoM): 0.64 pJ/conversion
• Effective Number of Bits (ENOB): 13.5
The FoM, calculated using the formula below, demonstrates the modulator's suitability for biomedical applications:

where NNN is the number of effective bits.
Comparative Analysis:
Table compares the proposed modulator's characteristics with other high-resolution modulators used in biomedical applications. The results highlight significant improvements in power consumption and accuracy, achieved through a well-defined design process. Reducing the capacitor value in newer CMOS technologies could further enhance power efficiency and FoM.

This study designed and simulated a second-order delta-sigma modulator for biomedical applications with an oversampling rate of 128 kHz and a resolution of 14 bits. The proposed modulator uses a gain amplifier similar to those employed in low-speed applications.
The measured power consumption is 800 nW, with flicker noise effectively mitigated using the CDS technique. System coefficients were optimized using the SCHREIER toolbox, resulting in a Nyquist-rate of 100 Hz, a sampling frequency of 12.8 kHz, and a maximum SNDR of 86 dB.
With an FoM of 0.64 pJ/conversion, the proposed modulator demonstrates significant potential for biomedical applications. Both theoretical and simulation results validate the modulator's performance and suitability.
DETAILED DESCRIPTION OF DIAGRAM
Figure 1: The conventional second order modulator
Figure 2: The optimized second order modulator.
Figure 3: The modified second order modulator.
Figure 4: The dynamic range curve of the optimized structure.
Figure 5: The graph of simulated SNDR according to the amplifier gain.
Figure 6: (a) An equivalent switching circuit for removing the flicker noise and (b) equivalent circuit in ø2.
Figure 7: The proposed switch capacitor structure.
Figure 8: The layout prototype of the proposed circuit. , Claims:1. High Performance Continuous Time Delta Sigma ADC for Biomedical Applications claims that it achieves an exceptionally low power consumption of 800 nW, making it ideal for energy-constrained biomedical applications such as wearable devices and implantable systems.
2. Demonstrates a dynamic range of 86 dB, ensuring accurate signal acquisition even in environments with high noise or low-amplitude signals.
3. Delivers a FoM of 0.64 pJ/conversion, placing it among the most efficient ADCs designed for biomedical signal processing.
4. Implements the design using 0.18 µm CMOS technology with an active area of 525 µm × 210 µm, providing a compact solution for space-sensitive applications.
5. Achieves an ENOB of 13.5, enabling high-precision data acquisition for biomedical signals, including ECG, EEG, and bioimpedance.
6. Operates reliably across extreme CMOS technology corners, from SS@85°C to FF@-40°C, ensuring consistent performance in diverse conditions.
7. Effectively suppresses flicker noise using a Correlated Double Sampling (CDS) technique, enhancing signal integrity for low-frequency biomedical signals.
8. Employs the SCHREIER toolbox to finely tune system coefficients, maximizing performance parameters such as signal-to-noise and distortion ratio (SNDR).
9. Validated through 500 Monte Carlo simulations, the design demonstrates minimal sensitivity to comparator offset mismatch with a standard deviation (σ) of 4.2 mV.
10. Tailored specifically for biomedical applications, with an oversampling rate of 128 kHz and a Nyquist bandwidth of 50 Hz, ensuring seamless integration with physiological signal acquisition systems.

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