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GPHL IO STANDARDS BASED ENERGY EFFICIENT VEDIC MULTIPLIER DESIGN ON FPGA
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GPHL IO STANDARDS BASED ENERGY EFFICIENT VEDIC MULTIPLIER DESIGN ON FPGA
ORDINARY APPLICATION
Published
Filed on 28 October 2014
Patent Information
| Application ID | 3064/DEL/2014 |
| Date of Application | 28/10/2014 |
Documents
| Name | Date |
|---|---|
| 3064-DEL-2014-Correspondence-150519-.pdf | 25/05/2019 |
| 3064-DEL-2014-Power of Attorney-150519-.pdf | 25/05/2019 |
| Description(Complete) [24-10-2015(online)].pdf | 24/10/2015 |
| 3064-DEL-2014-Form 1-121114.pdf | 12/02/2015 |
| 3064-DEL-2014-Power of Attorney-121114.pdf | 03/12/2014 |
| Form 26.pdf | 13/11/2014 |
| Form 3.pdf | 13/11/2014 |
| FORM 5.pdf | 13/11/2014 |
