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GATE-ALL-AROUND (GAA) TRANSISTORS WITH ADDITIONAL BOTTOM CHANNEL FOR REDUCED PARASITIC CAPACITANCE AND METHODS OF FABRICATION
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Abstract
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GATE-ALL-AROUND (GAA) TRANSISTORS WITH ADDITIONAL BOTTOM CHANNEL FOR REDUCED PARASITIC CAPACITANCE AND METHODS OF FABRICATION
PCT NATIONAL PHASE APPLICATION
Published
Filed on 29 September 2022
Patent Information
| Application ID | 202247055924 |
| Date of Application | 29/09/2022 |
Documents
| Name | Date |
|---|---|
| 202247055924-FORM 3 [29-03-2023(online)].pdf | 29/03/2023 |
| 202247055924-Proof of Right [10-01-2023(online)].pdf | 10/01/2023 |
| 202247055924-COMPLETE SPECIFICATION [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-DECLARATION OF INVENTORSHIP (FORM 5) [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-DRAWINGS [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-FORM 1 [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-POWER OF AUTHORITY [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-PRIORITY DOCUMENTS [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-STATEMENT OF UNDERTAKING (FORM 3) [29-09-2022(online)].pdf | 29/09/2022 |
| 202247055924-TRANSLATIOIN OF PRIOIRTY DOCUMENTS ETC. [29-09-2022(online)].pdf | 29/09/2022 |
