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FPGA IMPLEMENTATION OF LOW LATENCY ARCHITECTURE OF XGBOOST FOR INFERENCE AND METHOD THEREFOR
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Abstract
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FPGA IMPLEMENTATION OF LOW LATENCY ARCHITECTURE OF XGBOOST FOR INFERENCE AND METHOD THEREFOR
ORDINARY APPLICATION
Published
Filed on 27 January 2021
Patent Information
| Application ID | 202121003639 |
| Date of Application | 27/01/2021 |
Documents
| Name | Date |
|---|---|
| 202121003639-CLAIMS [21-11-2022(online)].pdf | 21/11/2022 |
| 202121003639-CORRESPONDENCE [21-11-2022(online)].pdf | 21/11/2022 |
| 202121003639-FER_SER_REPLY [21-11-2022(online)].pdf | 21/11/2022 |
| 202121003639-FORM 3 [21-11-2022(online)].pdf | 21/11/2022 |
| 202121003639-OTHERS [21-11-2022(online)].pdf | 21/11/2022 |
| 202121003639-FER.pdf | 09/09/2022 |
| 202121003639-FORM 3 [05-05-2022(online)].pdf | 05/05/2022 |
| 202121003639-ORIGINAL UR 6(1A) FORM 26-021121.pdf | 05/11/2021 |
| 202121003639-FORM-26 [22-10-2021(online)].pdf | 22/10/2021 |
| 202121003639-Covering Letter [21-10-2021(online)].pdf | 21/10/2021 |
| 202121003639-Form 1 (Submitted on date of filing) [21-10-2021(online)].pdf | 21/10/2021 |
| 202121003639-Power of Attorney [21-10-2021(online)].pdf | 21/10/2021 |
| Abstract1.jpg | 19/10/2021 |
| 202121003639-COMPLETE SPECIFICATION [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-DECLARATION OF INVENTORSHIP (FORM 5) [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-DRAWINGS [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-FIGURE OF ABSTRACT [27-01-2021(online)].jpg | 27/01/2021 |
| 202121003639-FORM 1 [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-FORM 18 [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-PROOF OF RIGHT [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-REQUEST FOR EXAMINATION (FORM-18) [27-01-2021(online)].pdf | 27/01/2021 |
| 202121003639-STATEMENT OF UNDERTAKING (FORM 3) [27-01-2021(online)].pdf | 27/01/2021 |
