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FA- IMPLEMENTATION: HIGH-THROUGHPUT FINITE FIELD MULTIPLIERS USING REDUCTANT BASIS FOR FPGA AND ASIC IMPLEMENTATIONS.
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FA- IMPLEMENTATION: HIGH-THROUGHPUT FINITE FIELD MULTIPLIERS USING REDUCTANT BASIS FOR FPGA AND ASIC IMPLEMENTATIONS.
ORDINARY APPLICATION
Published
Filed on 27 July 2021
Patent Information
| Application ID | 202141033754 |
| Date of Application | 27/07/2021 |
Documents
| Name | Date |
|---|---|
| 202141033754-FORM-9 [02-08-2021(online)].pdf | 02/08/2021 |
| 202141033754-COMPLETE SPECIFICATION [27-07-2021(online)].pdf | 27/07/2021 |
| 202141033754-DRAWINGS [27-07-2021(online)].pdf | 27/07/2021 |
| 202141033754-FORM 1 [27-07-2021(online)].pdf | 27/07/2021 |
| 202141033754-SEQUENCE LISTING [27-07-2021(online)].txt | 27/07/2021 |
