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Eliminating Parasitic Inductance in Semiconductor-Based Converters with A 3D Lattice Structure
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Eliminating Parasitic Inductance in Semiconductor-Based Converters with A 3D Lattice Structure
ORDINARY APPLICATION
Published
Filed on 14 June 2023
Patent Information
| Application ID | 202341040673 |
| Date of Application | 14/06/2023 |
Documents
| Name | Date |
|---|---|
| 202341040673-COMPLETE SPECIFICATION [14-06-2023(online)].pdf | 14/06/2023 |
| 202341040673-DECLARATION OF INVENTORSHIP (FORM 5) [14-06-2023(online)].pdf | 14/06/2023 |
| 202341040673-DRAWINGS [14-06-2023(online)].pdf | 14/06/2023 |
| 202341040673-FORM 1 [14-06-2023(online)].pdf | 14/06/2023 |
| 202341040673-FORM-9 [14-06-2023(online)].pdf | 14/06/2023 |
| 202341040673-POWER OF AUTHORITY [14-06-2023(online)].pdf | 14/06/2023 |
| 202341040673-REQUEST FOR EARLY PUBLICATION(FORM-9) [14-06-2023(online)].pdf | 14/06/2023 |
