EFFECT OF DIELECTRICS ON THE PERFORMANCE OF N-TYPE LATERAL JUNCTIONLESS TFET

Abstract

ABSTRACT The present invention relates in the field of electronics and more particularly determining the performance properties i.e., Transconductance (gm), energy band gap, parasitic capacitances (Cgs, Cgd, and Cgg), cut-off frequency (FT), Gain Bandwidth Product (GBWP), subthreshold slope (SS), Ion/Ioff current, and threshold voltage (VT) of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Specification

Description:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Effect of Dielectrics on the Performance of N-Type Lateral Junctionless TFET




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.


Effect of Dielectrics on the Performance of N-Type Lateral Junctionless TFET

Field of Invention:
The present invention relates in the field of electronics and more particularly determining the performance of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The need for more compact electronic gadgets is being driven by technological breakthroughs. Nevertheless, there are significant difficulties in shrinking traditional Field-Effect Transistors (FETs), such MOSFETs, to nanoscale sizes. These include more difficult manufacturing procedures and unfavorable performance traits like short-channel effects, which emphasize the demand for creative substitutes for transistors. With the use BTBT, TFETs are a promising experimental alternative to conventional FETs that may successfully handle problems like leakage current and ambipolar conduction. Furthermore, CMOS manufacturing techniques are still compatible with TFETs.
Despite their great potential, TFETs have a number of disadvantages, such as complicated production procedures and low on-state current. Scientists have created the junction-less TFET (JLTFET), a modified kind of TFET, to overcome these difficulties [9]. Unlike traditional p-n junctions, JLTFETs use a consistently high doping concentration across the drain, channel, and source regions. This technique gets around restrictions and successfully lowers short-channel effects, improving performance. This work aims to investigate the performance factors of HfO2, Al2O3, and SiO2 single- and dual-dielectric combinations in Junctionless Tunnel Field Effect Transistors (JLTFETs).
Therefore, there is need for analytical approach to evaluate the performance characteristics of different dielectric combinations among Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs).
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provides an analytical approach to determine the performance characteristics of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Summary of the Invention:
In an embodiment, the present invention provides a system and method to analyze and determine the performance characteristics of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates JLTFET 2-Dimension Structure Single Dielectric.
Figure 2: illustrates JLTFET 2-Dimension Structure Dual Dielectric.
Figure 3: illustrates Ids ~ Vgs plot for both single and dual dielectrics.
Figure 4: illustrates Band Energy plot for both single and dual dielectrics.
Figure 5: illustrates Transconductance (gm) plot for both single and dual dielectrics.
Figure 6: illustrates Gate's reliance on drain capacitance (Cgd) in both single and dual dielectrics.
Figure 7: illustrates Gate capacitance to the source (Cgs) plot for both single and dual dielectrics.
Figure 8: illustrates Total gate-to-gate capacitance curve (Cgg) for both single and dual dielectrics.
Figure 9: illustrates Subthreshold swing (SS) and ION/IOFF ratio for both single and dual dielectrics.
Figure 10: illustrates Threshold voltage (VT) for both single and dual dielectrics.
Figure 11: illustrates fT for both single and dual dielectrics
Figure 12: illustrates GBWP plot for both single and dual dielectrics.
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides an analytical approach to determine the performance characteristics of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

In an embodiment, Figures 1 and 2 both show the 2-dimensional structure of the disclosed SiGe/GaAs-JLTFET device. composition with a high band gap GaAs is used in the channel and drain regions, while band gap engineering is used to use low band gap composite SiGe in the source region. In order to stop leakage current, single and dual dielectrics with the same thickness are used at both gates in Figures 1 and 2. To isolate the polar gate (PG) and control gate (CG), a 2 nm gap is placed between them. The 2-D structure of the JLTFET, with SiGe at the source and GaAs at the channel and drain, is shown in the remaining portions of Figs. 1 and 2.
In Fig. 1, a single dielectric is used to handle leakage current through the gates, whereas Fig. 2 uses dual dielectrics at both gates. Figure 1 shows variations in the single dielectric material, HfO2/Al2O3/SiO2, while Figure 2 shows mixtures of these components. The technical details for these combinations are shown in Table I.
DEVICE CONSTRUCTION BOUNDS
SiGe/GaAs-JLTFET
Elements Size Dimensions
Source/Channel/Drain Length 20 nm
CG/PG Thickness 2 nm
HfO2/Al2O3/SiO2 Single Dielectric 2 nm
Dual Dielectric 1
Polar Gate Work Function 5.93 eV
Control Gate Work Function 4.5 eV
SiGe/GaAs Thickness 3 nm
Spacer height 2 nm
Spacer Width 2 nm

In the present invention, the Silvaco TCAD simulator has been used as primary modeling tool for the described device. It accurately captures the intricate physical processes involved in its operation. We specifically utilize the Band-to-Band Tunneling (BTBT) model to intricately represent recombination tunneling. This model incorporates boundaries at the channel/drain interface and establishes a quantum tunneling zone at the source/channel interface, enabling both forward and reverse tunneling. Additionally, we account for trap-assisted tunneling in the OFF state. Our simulation also incorporates Shockley-Read-Hall and Auger recombination models to precisely depict carrier recombination processes.

To quantitatively compute tunneling probabilities, we employ the Wentzel-Kramers-Brillouin method. Furthermore, we enhance simulation accuracy using Hansch's quantum confinement model. Throughout the simulation process, we solve carrier transport equations numerically, employing Gummel and Newton's technique, ensuring a comprehensive understanding of device behavior.

The present invention focuses on evaluating device characteristics by employing both single and dual dielectrics. We record the outcomes of these simulations for later comparison and based on the data obtained from simulations with various dielectric configurations.
When compared to other dual dielectric combinations and single dielectrics, the dual dielectric combination of HfO2 and Al2O3 performs better, as shown in Fig. 3, showing the maximum drain current (Ids). The lowest value was found for SiO2, and the maximum and lowest values differ significantly. In addition, the single dielectric HfO2 is the second-best performing material. Consequently, compared to alternative designs, the dual dielectric combination of HfO2 and Al2O3 provides the greatest current. We observed that the combinations of SiO2 in a dual dielectric makes the overall combination deliver lower drain current (Ids) and HfO2 is opposite of these and Al2O3 is moderated between them.

The energy band gap of a JLTFET's single and dual dielectrics is shown in Fig. 4. The graph shows that, out of all the dielectrics, the combination of Al2O3 and SiO2 has the smallest energy gap, whereas HfO2 has the largest band gap, measuring 6.5 eV. The band gap is an important factor in subthreshold swing, on/off current ratio, and switching speed, among other device performance parameters, since it greatly affects carrier tunneling across the junctionless channel.

Optimizing JLTFET designs for particular applications requires an understanding of and control over the interaction between dielectric materials and band gap, especially in low-power devices where lowering energy barriers for carrier transport is critical. Figure 5 illustrates the transconductance (gm) of both single and dual dielectrics in a JLTFET. Transconductance plays a crucial role in showcasing the behavior of a device at high frequencies, making it essential for RF performance. The transconductance value can be obtained using equation (1). Having a high value of gm is beneficial for improving RF performance. Through analysis of the graph, it is observed that HfO2 exhibits the highest gm, followed by the combination of HfO2 and Al2O3. Conversely, SiO2 displays the lowest transconductance value among all combinations.



From Fig. 6, it can observed that Single dielectric HfO2 has the highest Capacitance Cgd for overall gate voltage and the combination of HfO2 and Al2O3 is overtaken by a combination of HfO¬2 and SiO2 in capacitance value after gate voltage crossing 1.4 Volts. SiO2 reports the least Cgd value in the graph.

The capacitance Cgs as shown in Fig. 7. It observe the graph, the at-gate voltage value is less than 1 V, and the HfO2 displayed the highest capacitance value, but as it crosses the Vgs of 1 V, we can see that it has decreased exponentially to lowest in entire dielectrics and we see that SiO2 being achieved the highest Cgs value as the Vgs is increased.

Cgd and Cgs are two different Parasitic Capacitances, which are shown in Fig 6 and Fig 7. Figure 8 will show the total parasitic capacitance Cgg, which we can obtain from the equation 2.

Cgg = Cgd + Cgs (2)
The HfO2 Dielectric shows the highest total parasitic capacitance at the start, but at particular voltage Vgs, there is a gradual decrease in the capacitance value. Except for SiO2, all the single and dual dielectrics have shown a decrease in the capacitance value at different Vgs. SiO2 is only dielectric, which increases capacitance value as we increase the Vgs value.

The current on/off interaction (Ion/Ioff) and subthreshold oscillation (SS) are important parameter to determine any device capabilities. Fig.9 shows the bar graph of these parameters of single and dual dielectric combinations. Where low value of SS showcases the better switching capabilities, SiO2 shows the least value, whereas HfO2 has highest SS value.
The device efficiency is dependent on Ion/Ioff current, where the high value of the current ratio showcases the high Ion and low Ioff. Dual dielectric combination of Al2O3 and SiO2 has highest current ratio whereas SiO2 which has shown good subthreshold is showing least Ion/Ioff ratio which is not desired for good performance of device.

Fig 10. Shows the Threshold (VT) values when single and dual dielectric with there combinations are used in a JLTFET. The overall low subthreshold value is seen for HfO¬2 And the highest VT for SiO2. Low Threshold value shows the least power consumption and high switching speed. But it also requires stable threshold. So, we can't randomly say at which value threshold is good. It depends on the application of that device.

Fig.11 gives the information of Cut-off frequency of single and dual dielectric of a JLTFET. The fT determines the performance of any device at that frequency written in equation (3); after crossing fT, the performance of the device declines. So, it is desired that fT is high. HfO2 showcases the highest fT value, followed by a dielectric combination of HfO2 and Al2O3. SiO2 has the least cut-off frequency.



GBWP is a performance characteristic of a device where a device operates normally in that range of frequencies expressed in eqn (4). It is desired to be high so a device can perform in a large range of frequencies. From Fig. 12, the HfO2 combination of HfO2 and Al2O3 has shown exceptionally good performance in this category.

In conclusion, the present invention gives an overall study of the parameters affected by changing the dielectric of a Junionless Tunnel Field Effect Transistor (JLTFET). As the cost of device is also main factor while fabrication, HfO2 takes lead in overall parameters, but availability and fabrication wise HfO2 is costly and SiO2 underperforms in overall categories but it is cheaper and is abundant. As single dielectric materials show distinct advantages but combination of the Al2O3 and HfO2 gives an balanced performance. As, HfO¬2 despite showing high performance because of high parasitic capacitance values the stability is decreased and has a potential of underperforming. So, selecting an device from these dielectrics there should be a tradeoff for an desired application.
, Claims:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Effect of Dielectrics on the Performance of N-Type Lateral Junctionless TFET




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.


Effect of Dielectrics on the Performance of N-Type Lateral Junctionless TFET

Field of Invention:
The present invention relates in the field of electronics and more particularly determining the performance of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The need for more compact electronic gadgets is being driven by technological breakthroughs. Nevertheless, there are significant difficulties in shrinking traditional Field-Effect Transistors (FETs), such MOSFETs, to nanoscale sizes. These include more difficult manufacturing procedures and unfavorable performance traits like short-channel effects, which emphasize the demand for creative substitutes for transistors. With the use BTBT, TFETs are a promising experimental alternative to conventional FETs that may successfully handle problems like leakage current and ambipolar conduction. Furthermore, CMOS manufacturing techniques are still compatible with TFETs.
Despite their great potential, TFETs have a number of disadvantages, such as complicated production procedures and low on-state current. Scientists have created the junction-less TFET (JLTFET), a modified kind of TFET, to overcome these difficulties [9]. Unlike traditional p-n junctions, JLTFETs use a consistently high doping concentration across the drain, channel, and source regions. This technique gets around restrictions and successfully lowers short-channel effects, improving performance. This work aims to investigate the performance factors of HfO2, Al2O3, and SiO2 single- and dual-dielectric combinations in Junctionless Tunnel Field Effect Transistors (JLTFETs).
Therefore, there is need for analytical approach to evaluate the performance characteristics of different dielectric combinations among Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs).
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provides an analytical approach to determine the performance characteristics of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Summary of the Invention:
In an embodiment, the present invention provides a system and method to analyze and determine the performance characteristics of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates JLTFET 2-Dimension Structure Single Dielectric.
Figure 2: illustrates JLTFET 2-Dimension Structure Dual Dielectric.
Figure 3: illustrates Ids ~ Vgs plot for both single and dual dielectrics.
Figure 4: illustrates Band Energy plot for both single and dual dielectrics.
Figure 5: illustrates Transconductance (gm) plot for both single and dual dielectrics.
Figure 6: illustrates Gate's reliance on drain capacitance (Cgd) in both single and dual dielectrics.
Figure 7: illustrates Gate capacitance to the source (Cgs) plot for both single and dual dielectrics.
Figure 8: illustrates Total gate-to-gate capacitance curve (Cgg) for both single and dual dielectrics.
Figure 9: illustrates Subthreshold swing (SS) and ION/IOFF ratio for both single and dual dielectrics.
Figure 10: illustrates Threshold voltage (VT) for both single and dual dielectrics.
Figure 11: illustrates fT for both single and dual dielectrics
Figure 12: illustrates GBWP plot for both single and dual dielectrics.
Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides an analytical approach to determine the performance characteristics of Al2O3, SiO2, and HfO2 as Junctionless Tunnel Field Effect Transistors (JLTFETs) during the change in their single or dual dielectric.

In an embodiment, Figures 1 and 2 both show the 2-dimensional structure of the disclosed SiGe/GaAs-JLTFET device. composition with a high band gap GaAs is used in the channel and drain regions, while band gap engineering is used to use low band gap composite SiGe in the source region. In order to stop leakage current, single and dual dielectrics with the same thickness are used at both gates in Figures 1 and 2. To isolate the polar gate (PG) and control gate (CG), a 2 nm gap is placed between them. The 2-D structure of the JLTFET, with SiGe at the source and GaAs at the channel and drain, is shown in the remaining portions of Figs. 1 and 2.
In Fig. 1, a single dielectric is used to handle leakage current through the gates, whereas Fig. 2 uses dual dielectrics at both gates. Figure 1 shows variations in the single dielectric material, HfO2/Al2O3/SiO2, while Figure 2 shows mixtures of these components. The technical details for these combinations are shown in Table I.
DEVICE CONSTRUCTION BOUNDS
SiGe/GaAs-JLTFET
Elements Size Dimensions
Source/Channel/Drain Length 20 nm
CG/PG Thickness 2 nm
HfO2/Al2O3/SiO2 Single Dielectric 2 nm
Dual Dielectric 1
Polar Gate Work Function 5.93 eV
Control Gate Work Function 4.5 eV
SiGe/GaAs Thickness 3 nm
Spacer height 2 nm
Spacer Width 2 nm

In the present invention, the Silvaco TCAD simulator has been used as primary modeling tool for the described device. It accurately captures the intricate physical processes involved in its operation. We specifically utilize the Band-to-Band Tunneling (BTBT) model to intricately represent recombination tunneling. This model incorporates boundaries at the channel/drain interface and establishes a quantum tunneling zone at the source/channel interface, enabling both forward and reverse tunneling. Additionally, we account for trap-assisted tunneling in the OFF state. Our simulation also incorporates Shockley-Read-Hall and Auger recombination models to precisely depict carrier recombination processes.

To quantitatively compute tunneling probabilities, we employ the Wentzel-Kramers-Brillouin method. Furthermore, we enhance simulation accuracy using Hansch's quantum confinement model. Throughout the simulation process, we solve carrier transport equations numerically, employing Gummel and Newton's technique, ensuring a comprehensive understanding of device behavior.

The present invention focuses on evaluating device characteristics by employing both single and dual dielectrics. We record the outcomes of these simulations for later comparison and based on the data obtained from simulations with various dielectric configurations.
When compared to other dual dielectric combinations and single dielectrics, the dual dielectric combination of HfO2 and Al2O3 performs better, as shown in Fig. 3, showing the maximum drain current (Ids). The lowest value was found for SiO2, and the maximum and lowest values differ significantly. In addition, the single dielectric HfO2 is the second-best performing material. Consequently, compared to alternative designs, the dual dielectric combination of HfO2 and Al2O3 provides the greatest current. We observed that the combinations of SiO2 in a dual dielectric makes the overall combination deliver lower drain current (Ids) and HfO2 is opposite of these and Al2O3 is moderated between them.

The energy band gap of a JLTFET's single and dual dielectrics is shown in Fig. 4. The graph shows that, out of all the dielectrics, the combination of Al2O3 and SiO2 has the smallest energy gap, whereas HfO2 has the largest band gap, measuring 6.5 eV. The band gap is an important factor in subthreshold swing, on/off current ratio, and switching speed, among other device performance parameters, since it greatly affects carrier tunneling across the junctionless channel.

Optimizing JLTFET designs for particular applications requires an understanding of and control over the interaction between dielectric materials and band gap, especially in low-power devices where lowering energy barriers for carrier transport is critical. Figure 5 illustrates the transconductance (gm) of both single and dual dielectrics in a JLTFET. Transconductance plays a crucial role in showcasing the behavior of a device at high frequencies, making it essential for RF performance. The transconductance value can be obtained using equation (1). Having a high value of gm is beneficial for improving RF performance. Through analysis of the graph, it is observed that HfO2 exhibits the highest gm, followed by the combination of HfO2 and Al2O3. Conversely, SiO2 displays the lowest transconductance value among all combinations.



From Fig. 6, it can observed that Single dielectric HfO2 has the highest Capacitance Cgd for overall gate voltage and the combination of HfO2 and Al2O3 is overtaken by a combination of HfO¬2 and SiO2 in capacitance value after gate voltage crossing 1.4 Volts. SiO2 reports the least Cgd value in the graph.

The capacitance Cgs as shown in Fig. 7. It observe the graph, the at-gate voltage value is less than 1 V, and the HfO2 displayed the highest capacitance value, but as it crosses the Vgs of 1 V, we can see that it has decreased exponentially to lowest in entire dielectrics and we see that SiO2 being achieved the highest Cgs value as the Vgs is increased.

Cgd and Cgs are two different Parasitic Capacitances, which are shown in Fig 6 and Fig 7. Figure 8 will show the total parasitic capacitance Cgg, which we can obtain from the equation 2.

Cgg = Cgd + Cgs (2)
The HfO2 Dielectric shows the highest total parasitic capacitance at the start, but at particular voltage Vgs, there is a gradual decrease in the capacitance value. Except for SiO2, all the single and dual dielectrics have shown a decrease in the capacitance value at different Vgs. SiO2 is only dielectric, which increases capacitance value as we increase the Vgs value.

The current on/off interaction (Ion/Ioff) and subthreshold oscillation (SS) are important parameter to determine any device capabilities. Fig.9 shows the bar graph of these parameters of single and dual dielectric combinations. Where low value of SS showcases the better switching capabilities, SiO2 shows the least value, whereas HfO2 has highest SS value.
The device efficiency is dependent on Ion/Ioff current, where the high value of the current ratio showcases the high Ion and low Ioff. Dual dielectric combination of Al2O3 and SiO2 has highest current ratio whereas SiO2 which has shown good subthreshold is showing least Ion/Ioff ratio which is not desired for good performance of device.

Fig 10. Shows the Threshold (VT) values when single and dual dielectric with there combinations are used in a JLTFET. The overall low subthreshold value is seen for HfO¬2 And the highest VT for SiO2. Low Threshold value shows the least power consumption and high switching speed. But it also requires stable threshold. So, we can't randomly say at which value threshold is good. It depends on the application of that device.

Fig.11 gives the information of Cut-off frequency of single and dual dielectric of a JLTFET. The fT determines the performance of any device at that frequency written in equation (3); after crossing fT, the performance of the device declines. So, it is desired that fT is high. HfO2 showcases the highest fT value, followed by a dielectric combination of HfO2 and Al2O3. SiO2 has the least cut-off frequency.



GBWP is a performance characteristic of a device where a device operates normally in that range of frequencies expressed in eqn (4). It is desired to be high so a device can perform in a large range of frequencies. From Fig. 12, the HfO2 combination of HfO2 and Al2O3 has shown exceptionally good performance in this category.

In conclusion, the present invention gives an overall study of the parameters affected by changing the dielectric of a Junionless Tunnel Field Effect Transistor (JLTFET). As the cost of device is also main factor while fabrication, HfO2 takes lead in overall parameters, but availability and fabrication wise HfO2 is costly and SiO2 underperforms in overall categories but it is cheaper and is abundant. As single dielectric materials show distinct advantages but combination of the Al2O3 and HfO2 gives an balanced performance. As, HfO¬2 despite showing high performance because of high parasitic capacitance values the stability is decreased and has a potential of underperforming. So, selecting an device from these dielectrics there should be a tradeoff for an desired application.

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