DUAL-SERIES SINGLE-PARALLEL SWITCHED CAPACITOR MULTILEVEL INVERTER SYSTEM AND METHOD THEREOF

Abstract

The present invention discloses a single source based Dual-Series Single-Parallel Switched Capacitor (DSSP-SC) eleven-level multilevel inverter system (100). The present invention combines a single-phase switched capacitor based multilevel inverter unit with two capacitors in series and one in parallel to reduce the number of switching devices and overall cost. Additionally, the system (100) can produce an eleven-level output voltage using a single dc voltage source, replacing all other voltage sources with switched capacitors. Notably, the system (100) does not require a filter circuit to minimize current harmonics, as these are effectively minimized by the eleven-level waveform. The system (100) also utilizes a low frequency switching scheme to decrease losses, leading to a more efficient and cost-effective solution. The system (100) is highly suitable for single-phase applications such as photovoltaic systems (100), electric vehicles, microgrids and residential uses, effectively reduces the cost of active sources and system (100) complexity by achieving higher voltage levels with fewer components.

Specification

Description:FIELD OF INVENTION
The present disclosure generally relates to a dual-series single-parallel switched capacitor multilevel inverter system and method. More particularly, the present disclosure relates to a dual-series single-parallel switched capacitor multilevel inverter system and method for generating a single-phase, eleven-level voltage output.
BACKGROUND
In solar power conversion systems, for instance, number of solar panels are linked either in series or in parallel. The output of these solar panels may fluctuate due to a variety of factors, including the time of day, location, and sun tracking capability. To control the output of the solar panels, a DC/DC converter is used to obtain a controlled output voltage. If the power utility goes out or the solar panels are used as an off-grid power source, the output of the solar panels is used to charge a backup battery that powers the connected loads.
To convert solar energy into utility electricity with high power and high efficiency, a variety of multilevel inverter topologies are used. These multilevel inverters can be categorized based on topology differences into three groups: Neutral Point Clamped (NPC) inverter, flying capacitor multilevel inverters, and cascaded H-bridge multilevel inverters. Each of these inverters can utilize a variety of pulse width modulation (PWM) strategies, including space vector modulation, selective harmonic elimination PWM, sinusoidal PWM (SPWM), and others. Despite their varied uses, these inverters have their own set of drawbacks, such as a non-uniform harmonic profile of voltage, which affects their overall efficiency and performance.
Traditional multilevel inverters require a greater number of components for achieving higher voltage levels. Additional voltage balancing circuits are needed to ensure that the voltage levels remain stable and balanced without requiring additional control mechanisms. This leads to improved space requirements and increased cost and complexity of the system. Furthermore, these inverters often require complex control mechanisms and additional components, making them less efficient and more costly to implement and maintain. These challenges highlight the need for improved multilevel inverter systems that can achieve higher voltage levels with fewer components and simpler control mechanisms.
In the prior art, US10886831B2 discloses a multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor is configured to switch the plurality of low voltage MOSFET transistors in each bank at multiple times during each cycle. In another prior art, US10903656B2, a system comprises a first five-level inverter connected between a DC power source and an AC grid, a second five-level inverter connected between the DC power source and the AC grid, and a third five-level inverter connected between the DC power source and the AC grid. Each five-level inverter comprises a first boost apparatus and a second boost apparatus. However, these prior arts are not capable of decreasing the number of switches for generating multi-level voltage outputs with reduced total harmonic distortions. The complexity of the circuitry in these systems is also a significant issue.
Therefore, there is a need to overcome the problems discussed above. The ideal solution would be a system that can generate a maximum number of voltage outputs by utilizing a minimal number of switches. This system should be suitable for high power quality PV system application using reduced components and should also be capable of reducing total harmonic distortions, making it more efficient and cost-effective. The need for such a system is underscored by the increasing demand for efficient and reliable renewable energy generation systems.
SUMMARY
A dual-series single-parallel switched capacitor (DSSP-SC) multilevel inverter system in accordance with the present disclosure comprises a first unit comprising the DSSP-SC paired with a second unit comprising an h-bridge unit connected to a single-phase load. The paired connection of the first unit with the second unit acts as a means for increasing non-zero voltage levels produced by the system by 2.5 times of the voltage levels provided by the series-parallel charging of capacitors along with reduced number of switches and voltage stress on the switches. Further, each of the said unit is installed with a plurality of switches utilized for performing switching of circuit formed by pairing said units in parallel with each other. Furthermore, a microcontroller is electronically paired with the said units to trigger gate signals from each of the said switches by generating switching pulses for each of the said switches. The microcontroller evaluates switching time instants by using half height method to perform switching within the said units in an appropriate manner required to get an eleven-level voltage output with reduced harmonics as well as reduced number of switches.
A method to generate a multilevel voltage output of the system in accordance with the present disclosure, the method comprising pairing the first unit with the second unit in parallel connection required to increase the voltage levels of the output voltage of the system. Further, the method includes supplying DC power from the DC voltage sources to said inverter units. The DC voltage sources are either symmetric or asymmetric in nature required to control harmonic profile of the voltage output generated by the system. Furthermore, the method involves evaluating switching time instants for each of the phase by the microcontroller by utilizing the half height method. The microcontroller generates switching patterns for the switches. Moreover, the method comprises transmitting of generated switching signals to the switches by the microcontroller. After the switches receives the signals, the gate control signals for the said switches are generated and simultaneously the microcontroller controls instant time in between signaling by using half height method resulting in generation of the eleven-level voltage output fed to a single-phase load as per a user's requirement.
In an embodiment of the present disclosure, the first unit comprises a first half-bridge cell, a second half-bridge cell, a third half-bridge cell and a DC voltage source. The first half-bridge cell comprises a capacitor C1 and switches S2 and S3. Further, the second half-bridge cell comprises a capacitor C2 and switches S1 and S5. Furthermore, the third half-bridge cell comprises a capacitor C3 and switches S7 and S8.
In an embodiment of the present disclosure, the first half-bridge cell and the second half-bridge cell are connected in series, the series connected first half-bridge cell and the second half-bridge cell are connected in parallel with the third half-bridge cell.
In an embodiment of the present disclosure, the microcontroller controls switching timing of the switches for each phase of the said units required to get desired output.
BRIEF DESCRIPTION OF FIGURES
The foregoing and other features of this disclosure will become fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several embodiments in accordance with the disclosure and are, therefore, not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings, in which:
FIG. 1 illustrates a circuit diagram of a dual-series single-parallel switched capacitor (DSSP-SC) multilevel inverter system in accordance with the present disclosure;
FIG. 2 illustrates an exemplary flowchart of a method of generating a single-phase eleven-level voltage output in accordance with the present disclosure;
FIG. 3 illustrates an exemplary representation of the single-phase eleven-level output voltage waveform of the DSSP-SC multilevel inverter system in accordance with the present disclosure;
FIG. 4 illustrates an exemplary representation of the single-phase eleven-level output current waveform of the DSSP-SC multilevel inverter system in accordance with the present disclosure;
FIG. 5 illustrates an exemplary representation of the single-phase eleven-level output voltage and current waveforms of the DSSP-SC multilevel inverter system with inductive load in accordance with the present disclosure;
FIG. 6 illustrates an exemplary representation of a harmonic analysis plot of a phase voltage waveform in accordance with the present disclosure;
FIG. 7 illustrates an exemplary representation of the harmonic analysis plot of a current waveform for inductive (RL) load in accordance with the present disclosure;
FIG. 8 illustrates an exemplary representation of an output voltage waveform across a first half-bridge cell in accordance with the present disclosure;
FIG. 9 illustrates an exemplary representation of an output voltage waveform across a second half-bridge cell in accordance with the present disclosure; and
FIG. 10 illustrates an exemplary representation of an output voltage waveform across a third half-bridge cell in accordance with the present disclosure.
DETAILED DESCRIPTION
Embodiments of the present disclosure are best understood by reference to the description set forth herein. All the aspects described herein will be better appreciated and understood when considered in conjunction with the following descriptions. It should be understood, however, that the following descriptions, while indicating preferred aspects and numerous specific details thereof, are given by way of illustration only and should not be treated as limitations. Changes and modifications may be made within the scope herein without departing from the spirit and scope thereof, and the present disclosure herein includes all such modifications.
Several aspects of the present disclosure are disclosed herein. It is to be understood that these aspects may or may not overlap with one another. Thus, part of one aspect may fall within the scope of another aspect, and vice versa. Each aspect is illustrated by a number of embodiments, each of which in turn, can include one or more specific embodiments. It is to be understood that the embodiments may or may not overlap with each other. Thus, part of one embodiment, or specific embodiments thereof, may or may not fall within the ambit of another, or specific embodiments thereof, and vice versa.
A broad framework of the principles will be presented by describing various embodiments of this disclosure using exemplary aspects. The terms "one embodiment" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. For clarity and ease of description, each aspect includes only a few embodiments. Different embodiments from different aspects may be combined or practiced separately, to design a customized process or product depending upon application requirements. Many different combinations and sub-combinations of a few representative processes or structures shown within the broad framework of this disclosure, that may be apparent to those skilled in the art but not explicitly shown or described, should not be construed as precluded.
The present invention relates to a single-phase eleven-level multilevel inverter system 100 which generates maximum voltage level outputs, i.e., eleven levels by utilizing minimum number of switches, DC sources and reduced voltage stress on the switches resulting in simpler circuit, faster switching, reduced Total Harmonic Distortion (THD) without utilizing any additional filter circuit, production of high-power quality single-phase voltage waveforms as well as a cost-effective system 100.
FIG. 1 illustrates a circuit diagram of a dual-series single-parallel switched capacitor (DSSP-SC) multilevel inverter system 100 in accordance with the present disclosure. The DSSP-SC multilevel inverter system 100 is configured to generate a single-phase eleven-level AC voltage waveform. The DSSP-SC multilevel inverter system 100 comprises a first unit and a second unit. The first unit comprises the DSSP-SC and the second unit comprises an h-bridge unit connected to a single-phase load. The first unit comprises a first half-bridge cell, a second half-bridge cell, a third half-bridge cell and a DC voltage source. The first half-bridge cell comprises a capacitor C1 and switches S2 and S3, the second half-bridge cell comprises a capacitor C2 and switches S1 and S5, and the third half-bridge cell comprises a capacitor C3 and switches S7 and S8. The capacitors C1, C2 and C3 acts as DC voltage sources of magnitudes V/2, V/2 and V respectively, V being the magnitude of the DC voltage source. The first half-bridge cell and the second half-bridge cell are connected in series. The said series connection is connected in parallel with the third half-bridge cell. The first unit is paired with the second unit as a means to increase non-zero voltage levels of the system 100 by 2.5 times of series-parallel connection of capacitors with the help of symmetric and asymmetric charging of capacitors. The said connection also reduces number of switches and voltage stress on the switches. Further, each of the said unit is installed with a plurality of switches utilized for performing switching of circuit formed by pairing said units in parallel with each other. A microcontroller is configured to be electronically paired with the said units to trigger gate signal from each of the said switches by generating switching pulses for each of the said switches. Moreover, the microcontroller evaluates switching time instants by using half-height method to perform switching within the said units in an appropriate manner required to get an eleven-level voltage output with reduced harmonics as well as reduced number of switches.
The system 100 comprises a charging phase, a balancing phase and a discharging phase that are configured for charging, balancing, and discharging the capacitors C1, C2 and C3 respectively.
Charging phase of Capacitors C1, C2 and C3:
During the charging phase, the capacitors C1 and C2 are charged simultaneously with a half value of the input voltage, i.e., Vdc/2. The charging of C1 and C2 occurs via keeping switches S2, S3, S5 and S8 closed. The capacitor C3 is isolated from the circuit via keeping the switch S7 opened. Also, during the charging of the capacitor C3, capacitors C1 and C2 are isolated from the circuit by keeping switches S1, S2, S3, S4 and S5 opened and keeping switches S7 and S8 opened. Hence, the capacitor C3 is charged to a full value of the input voltage. Table 1 provides the switching table for charging of the capacitors to particular voltage levels:

Table 1: representing switching in the DSSP-SC multilevel inverter system.
Discharging phase of Capacitors C1, C2 and C3:
During the discharging phase, the capacitors C1, C2 and C3 discharges at the load. Further, the circuit comprise a total of twelve switches along with three capacitors, one diode and a voltage source. The first half bridge cell, the second half bridge cell and the third half bridge cell comprise eight switches: S1, S2, S3, S4, S5, S6, S7 and S8. The load is coupled via four switches (T1, T2, T3 and T4). Further, different voltage levels can be achieved at the load via providing different signals to these switches. Also, a positive voltage level is obtained by closing T1 and T4, whereas negative level is obtained by closing T2 and T3. Further, a zero voltage at the output is achieved by keeping switches T1 and T2 closed.
Balancing phase of Capacitors C1, C2 and C3:
In order to balance the voltage levels across C1, C2 and C3, the capacitors C1 and C2 have been charged to Vdc/2 and C3 is charged to Vdc. Further for ensuring balancing of the capacitors C1, C2 and C3, the switch S2 is closed thereby connecting C2 in series with C1, to ensure Vdc/2 voltage across both C1 and C2. Further, the switches S1, S3 and S7 are turned off and D1 is reverse biased which balances the voltage levels across C1, C2 and C3.
In an embodiment of the present disclosure, the microcontroller controls the switching timing of the switches for each phase of the said units required to get desired output.
In an embodiment of the present disclosure, switch angles are determined by using half height method to produce the switching and thus an improved low THD output waveform is obtained.
FIG. 2 illustrates an exemplary flowchart of a method 200 of generating single-phase eleven-level voltage output in accordance with the present disclosure. The method 200 is configured to be performed on the dual-series single-parallel switched capacitor (DSSP-SC) multilevel inverter system 100.
In step 201, the method 200 comprises pairing the first unit with the second unit in the parallel connection required to increase the voltage levels of the output voltage of the system 100. The first unit comprises a DSSP-SC and the second unit comprises the h-bridge unit connected to a single-phase load. Further, the DSSP-SC comprises the first half-bridge cell, the second half-bridge cell and the third half-bridge cell.
In step 203, the method 200 involves supplying DC power from the DC voltage sources to said inverter units. The DC voltage sources are either symmetric or asymmetric in nature so as to control the harmonic profile of the voltage output generated by the system 100.
In step 205, the method 200 includes evaluating the switching time instants for each of the phase by the microcontroller by utilizing the half height method. Further, the microcontroller generates switching patterns for the switches.
In step 207, the method 200 comprises transmitting of generated switching signals to the switches by the microcontroller. On receiving the switching signals by the microcontroller, gate control signals for the said switches are generated. Further, the instant time in between signaling is controlled simultaneously by the microcontroller using the half height method, thereby resulting in the generation of the eleven-level voltage output fed to a single-phase load as per a user's requirement.
Further, the half-height method is used for the computation of switching angles for proposed single-phase eleven-level multilevel inverter system 100. It is low switching frequency method. In this method, when the value of sine function increases to the half-height of the nearest level, the switch angle is set and thus a better low THD output waveform obtained.
FIG. 3 illustrates an exemplary representation of the single-phase eleven-level output voltage waveform of the DSSP-SC multilevel inverter system 100 in accordance with the present disclosure. The single-phase voltage waveform is represented in terms of varying amplitudes of voltage waveform at corresponding instants of time. The single-phase eleven-level output voltage of the DSSP-SC system 100 comprises five positive voltage levels, five negative voltage levels and a ground level. The peak positive value of the voltage waveform is 60V and the peak negative value is -60V as can be seen from Fig. 3. The voltage waveform is repeating with respect to a time period, i.e., 0.02 seconds. The single-phase eleven-level voltage waveform closely resembles a sinusoidal AC voltage waveform, thereby achieving desired functions of an inverter.
FIG. 4 illustrates an exemplary representation of the single-phase eleven-level output current waveform of the DSSP-SC multilevel inverter system 100 in accordance with the present disclosure. The single-phase current waveform is represented in terms of a varying amplitude of the current waveform with respect to time. The peak positive value or the current waveform is approximately 0.75 Ampere, and the peak negative value is -0.75 Ampere. Further, the current waveform is repeating and is having varying amplitudes with respect to the time. Also, the single-phase eleven level current waveform approximates the sinusoidal AC current waveform for inductive load.
FIG. 5 illustrates an exemplary representation of the single-phase eleven-level output voltage and current waveforms of the DSSP-SC multilevel inverter system 100 with inductive load in accordance with the present disclosure. The single-phase eleven level output voltage and current waveforms for inductive loads are similar to the waveforms for other loads. Also, the produced single-phase voltage and current waveforms are also similar to the sinusoidal AC voltage waveform. Further, the current waveform lags behind the voltage waveform for the inductive load.
FIG. 6 illustrates an exemplary representation of a harmonic analysis plot of a phase voltage waveform in accordance with the present disclosure. The percentage of total harmonic distortion (THD) of the single-phase eleven-level voltage waveform is found to be 6.05 percent only, up to 50th order harmonics. The harmonic analysis plot is corresponding to the magnitude of percentage of fundamental versus harmonic order. Further, the fundamental at 50 Hz is 56.97. Also, the harmonic profile up to 50th order harmonics can be achieved without requiring any additional filter circuit.
FIG. 7 illustrates an exemplary representation of the harmonic analysis plot of a current waveform for inductive (RL) load in accordance with the present disclosure. The THD for the current waveform of the inductive load is 1.52 percent only, up to 50th order harmonics. Further, the current harmonics are suppressed more significantly when the load is inductive. Also, the fundamental at 50 Hz is 0.6979.
FIG. 8-10 illustrate an exemplary representations of output voltage waveforms across the first half-bridge cell, the second half-bridge cell and the third half-bridge cell respectively in accordance with the present disclosure. The first half-bridge cell, the second half-bridge cell and the third half-bridge cell comprises the capacitor C1, C2 and C3 respectively. During the charging of the capacitors, the capacitor C1 and C2 are charged together to the half of the input voltage, Vdc. The capacitor C3 is charged to the full value of the input voltage, Vdc. Fig. 8 represents the output voltage waveform of the first half-bridge cell in terms of the voltage versus time. The output voltage represents a square wave having two voltage levels, i.e., 12V (approx.) and 35V (approx.). Fig. 9 represents the output voltage waveform of the second half-bridge cell in terms of the voltage versus time. The output voltage represents a square wave having two voltage levels, i.e., 12V (approx.) and 24V (approx.). Fig. 10 represents the output voltage waveform of the third half-bridge cell in terms of the voltage versus time. The output voltage represents a square wave having three voltage levels, i.e., 0V, 12V (approx.) and 24V (approx.)
Accordingly, the present disclosure is advantageous over the prior existing technologies in terms of offering novel, effective and unique characteristics. Conventional multilevel inverters utilize a greater number of switching components thereby making the system complex, bulky and expensive. The conventional system requires more space for acquiring the switching components therewithin. This increases the space requirements, thereby having an increased size of the multilevel inverter system. The existing multilevel inverter systems utilize additional control mechanisms for voltage balancing for stabilizing the voltage levels. The present disclosure provides solution to problems posed by the conventional systems by providing a simple, efficient, cost-effective multilevel inverter system 100 with reduced size and space requirements. Further, the present disclosure provides a dual-series single-parallel switched capacitor (DSSP-SC) eleven level multilevel inverter system 100 which improves the power quality of generated output voltage in terms of total harmonic distortion. The multilevel inverter system 100 of the present invention achieves excellent harmonic profile up to 50th order harmonics. Furthermore, in comparison to the traditional systems, the DSSP-SC of the present disclosure provides higher voltage level outputs with fewer switching components. The present invention utilizes only a single dc source for producing 2.5 times of voltage level with series parallel connection of capacitors for providing symmetric and asymmetric number of voltage levels. Moreover, the present disclosure provides switched capacitor topology which provides voltage balancing for the capacitors, thereby ensuring stability and balance of the voltage outputs without requiring any additional circuits. The afore-mentioned self-balancing feature of the system 100 improves the reliability and performance of the multilevel inverter system 100. Additionally, the present invention provides reduced number of switching components as well as the voltage stress on the switching components. The present invention utilizes low frequency switching scheme and half-height method approach to decrease losses caused by switching frequency and utilized in single dc source applications, i.e., electric vehicles, microgrid, residential and renewable energy source applications.
Although the present disclosure has been described in terms of certain preferred embodiments, various features of separate embodiments can be combined to form additional embodiments not expressly described. Moreover, other embodiments apparent to those of ordinary skill in the art after reading this disclosure are also within the scope of this disclosure. Furthermore, not all the features, aspects and advantages are necessarily required to practice the present disclosure. Thus, while the above detailed description has shown, described, and pointed out novel features of the disclosure as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the apparatus or process illustrated may be made by those of ordinary skill in the technology without departing from the spirit of the disclosure. The disclosures may be embodied in other specific forms not explicitly described herein. The embodiments described above are to be considered in all respects as illustrative only and not restrictive in any manner.
, C , Claims:1. A dual-series single-parallel switched capacitor (DSSP-SC) multilevel inverter system (100), the system (100) comprises:
a first unit comprising the DSSP-SC paired with a second unit comprising an h-bridge unit connected to a single-phase load, as a means to increase non-zero voltage levels of the system (100) by 2.5 times of series-parallel connection of capacitors with the help of symmetric and asymmetric charging of capacitors along with reduced number of switches and voltage stress on the switches, wherein each of the said unit is installed with a plurality of switches utilized for performing switching of circuit formed by pairing said units in parallel with each other; and
a microcontroller electronically paired with said units to trigger gate signal from each of the said switches by generating switching pulses for each of the said switches, wherein the microcontroller evaluates switching time instants by using half height method to perform switching within the said units in an appropriate manner required to get an eleven-level voltage output with reduced harmonics as well as reduced number of switches.
2. The system (100) as claimed in claim 1, wherein the first unit comprises a first half-bridge cell, a second half-bridge cell, a third half-bridge cell, and a DC voltage source, wherein the first half-bridge cell comprises a capacitor C1 and switches S2 and S3, the second half-bridge cell comprises a capacitor C2 and switches S1 and S5, and the third half-bridge cell comprises a capacitor C3 and switches S7 and S8.
3. The system (100) as claimed in claim 2, wherein the capacitor C1, C2, and C3 acts as DC voltage sources of magnitudes V/2, V/2, and V respectively, V being the magnitude of the DC voltage source.
4. The system (100) as claimed in claim 2, wherein the first half-bridge cell and the second half-bridge cell are connected in series, the series connected first half-bridge cell and the second half-bridge cell are connected in parallel with the third half-bridge cell.
5. The system (100) as claimed in claim 1, wherein the microcontroller controls switching timing of the switches for each phase of the said units required to get desired output.
6. The system (100) as claimed in claim 1, wherein the system (100) comprises a charging phase, a balancing phase, and a discharging phase configured to charge, balance, and discharge capacitors C1, C2 and C3.
7. The system (100) as claimed in claim 1, wherein switch angles are determined by using half height method to produce the switching signals and thus an improved low THD output waveform is obtained.
8. A method (200) to generate a multilevel voltage output of the system (100) as claimed in claim 1, the method (200) comprising:
pairing the first unit with the second unit in the parallel connection required to increase the voltage levels of the output voltage of the system (100);
supplying DC power from the DC voltage sources to said inverter units, wherein the DC voltage sources are either symmetric or asymmetric in nature required to control harmonic profile of the voltage output generated by the system (100);
evaluating switching time instants for each of the phase by the microcontroller by utilizing the half height method, wherein the microcontroller generates switching patterns for the switches; and
transmitting of generated switching signals to the switches by the microcontroller, wherein upon receiving the signals, gate control signals for said switches are generated and simultaneously, said microcontroller controls instant time in between signaling by using said half height method results in generation of said eleven-level voltage output fed to a single-phase load as per a user's requirement.
9. The method (200) as claimed in claim 8, wherein the first unit comprises a first half-bridge cell, a second half-bridge cell, a third half-bridge cell, and a DC voltage source, wherein the first half-bridge cell comprises a capacitor C1 and switches S2 and S3, the second half-bridge cell comprises a capacitor C2 and switches S1 and S5, and the third half-bridge cell comprises a capacitor C3 and switches S7 and S8.
10. The method (200) as claimed in claim 8, wherein the capacitor C1, C2, and C3 acts as the DC voltage sources with magnitudes of V/2, V/2, and V respectively, V being the magnitude of the DC voltage source.

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