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DESIGN OF POWER GATED DOUBLE EDGE TERIGGERED FLIP FLOP USING SLEEP TRANSISTOR TECHNIQUE (PG-STDETFF)
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DESIGN OF POWER GATED DOUBLE EDGE TERIGGERED FLIP FLOP USING SLEEP TRANSISTOR TECHNIQUE (PG-STDETFF)
ORDINARY APPLICATION
Published
Filed on 3 January 2017
Patent Information
| Application ID | 201741000167 |
| Date of Application | 03/01/2017 |
Documents
| Name | Date |
|---|---|
| 201741000167-Annexure [19-01-2024(online)].pdf | 19/01/2024 |
| 201741000167-Written submissions and relevant documents [19-01-2024(online)].pdf | 19/01/2024 |
| 201741000167-Correspondence to notify the Controller [13-12-2023(online)].pdf | 13/12/2023 |
| 201741000167-US(14)-HearingNotice-(HearingDate-05-01-2024).pdf | 13/12/2023 |
| 201741000167-COMPLETE SPECIFICATION [25-03-2020(online)].pdf | 25/03/2020 |
| 201741000167-DRAWING [25-03-2020(online)].pdf | 25/03/2020 |
| 201741000167-FER_SER_REPLY [25-03-2020(online)].pdf | 25/03/2020 |
| 201741000167-AMENDED DOCUMENTS [06-03-2020(online)]-1.pdf | 06/03/2020 |
| 201741000167-AMENDED DOCUMENTS [06-03-2020(online)].pdf | 06/03/2020 |
| 201741000167-FORM 13 [06-03-2020(online)]-1.pdf | 06/03/2020 |
| 201741000167-FORM 13 [06-03-2020(online)].pdf | 06/03/2020 |
| 201741000167-RELEVANT DOCUMENTS [06-03-2020(online)]-1.pdf | 06/03/2020 |
| 201741000167-RELEVANT DOCUMENTS [06-03-2020(online)].pdf | 06/03/2020 |
| 201741000167-FER.pdf | 25/09/2019 |
| Form 9_Earlier Publication_30-05-2017.pdf | 30/05/2017 |
| Claims_As Filed_03-01-2017.pdf | 03/01/2017 |
| Correspondence by Agent_Filing Patent_03-01-2017.pdf | 03/01/2017 |
| Description Complete_As Filed_03-01-2017.pdf | 03/01/2017 |
| Drawings_As Filed_03-01-2017.pdf | 03/01/2017 |
| Form18_Normal Request_03-01-2017.pdf | 03/01/2017 |
| Form1_As Filed_03-01-2017.pdf | 03/01/2017 |
| Form2 Title Page_Complete_03-01-2017.pdf | 03/01/2017 |
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