Cross switched H-Bridge multilevel inverter

Abstract

An expanding field of study in power electronic circuits and applications is multilevel inverters. Among its many benefits are a near-sinusoidal output voltage, a lower peak inverse voltage (PIV), a lower total harmonic distortion (THD), and a lower dv/dt stress. However, there are also other related issues, like price, size complexity, and voltage imbalance in the capacitor. Here, the problems of excessive switching and unbalanced capacitor voltage are addressed using a unique nine-level inverter scheme. There are many benefits to the suggested system. The voltage imbalance issue is resolved, and the cost, size, and complexity are decreased. Additionally, there is less voltage stress across the switches. The switches' power loss distribution is ideal. Thus, the system's efficiency has increased. As a result, the system performs better overall. The system works effectively with a variety of loads, including motor, inductive, and resistive loads. A single-phase induction motor's stator voltage speed control has also been accomplished with success. The switching pulses have been created using the pulse width modulation (PWM) technology.

Specification

Description:Abstract:
An expanding field of study in power electronic circuits and applications is multilevel inverters. Among its many benefits are a near-sinusoidal output voltage, a lower peak inverse voltage (PIV), a lower total harmonic distortion (THD), and a lower dv/dt stress. However, there are also other related issues, like price, size complexity, and voltage imbalance in the capacitor. Here, the problems of excessive switching and unbalanced capacitor voltage are addressed using a unique nine-level inverter scheme. There are many benefits to the suggested system. The voltage imbalance issue is resolved, and the cost, size, and complexity are decreased. Additionally, there is less voltage stress across the switches. The switches' power loss distribution is ideal. Thus, the system's efficiency has increased. As a result, the system performs better overall. The system works effectively with a variety of loads, including motor, inductive, and resistive loads. A single-phase induction motor's stator voltage speed control has also been accomplished with success. The switching pulses have been created using the pulse width modulation (PWM) technology.

Description:
Multilevel inverters (MLIs) have drawn a lot of interest lately. Their near-sinusoidal staircase output voltage waveforms, increased efficiency, decreased total harmonic distortion (THD), decreased dv/dt stresses across switches, and decreased peak inverse voltage (PIV) are just a few of their appealing characteristics. They are widely employed in industrial applications, including renewable energy, micro grid applications, and motor drivers. Neutral-point-clamped (NPC), flying capacitor, and cascaded H-Bridge (CHB) are the three primary categories into which conventional MLIs fall. More power switches and clamp diodes are needed by NPC in order to generate more output levels. Furthermore, a capacitor might potentially have an imbalanced voltage issue. Similar to this, a flying capacitor type MI requires a lot of capacitors in order to provide a lot of different output voltage levels. The total cost will go up as a result. Furthermore, high-value capacitors are required in low-frequency applications. NPC is superior to FC in this instance. Unlike NPC and FC type MLIs, cascaded H-Bridge (CHB) MLIs have low voltage stress and don't need a clamping diode. Each capacitor's voltage can be automatically balanced without the need for extra auxiliary circuits or balance circuits thanks to an intrinsic self-voltage balancing capacity (MLI) that was proposed. This novel topology MLI can be used to derive FC and NPC; however it has limits and calls for higher power devices. The cascaded H-Bridge (CHB) MLIs with decreased components were proposed. The issue is that each H-Bridge in cascaded units needs a large number of independent dc sources. Presented a standard series hybrid MLI to reduce THD and produce more output voltage levels.
In order to provide combined benefits, such as the flexibility of FC and NPC, an active neutral point clamped (ANPC hybrid inverter was presented
the resilience of NPC. In order to reduce voltage stress on the switches and enable self-balancing of capacitor voltage without the need for extra circuits, a selective harmonic elimination technique has been developed. However, the system's drawback is that it creates a complicated circuit with a lot of parts.
Three 9-level inverters using switch capacitor (SC) networks have been proposed. Although the systems of are straightforward, the input voltage is always divided by means of a series connection of capacitors. As a result, the output currents in the positive and negative halves of the cycle differ cycle. As a result, there is an imbalanced voltage across the capacitors. Although the issue of uneven voltage was fixed, a significant number of power switches were still needed. Two steps make up the suggested nine-level inverter scheme. Each stage's increased power loss results in a reduction in the efficiency of these systems.
With the benefits of SC methods, the numbers of 7-level multilevel inverters have been proposed. Especially, in only one capacitor is used. Due to which no voltage balancing problem is there, but two different value DC voltage sources are needed. The systems proposed are obtained by three H-bridges connected in cascaded connection with two switches, both switches are bidirectional. They have the benefits of cascaded H-Bridge (CHB) but sixteen switches are needed. Bidirectional switches result in a greater distribution of power loss, which reduces efficiency and raises system costs. A step-up series-based inverter (MLI) system is introduced, along with switched-capacitor (SC) devices. It can be used as a source of high frequency (HF) power. However, a lot of sources and components are needed to generate the higher level.
The aforementioned difficulties have led to the proposal of new SC-based 9 level inverters. Nine switches, two capacitors, two power diodes, and a single DC voltage source make up this system. The new suggested multilevel inverter has produced more output voltage levels with fewer components than the current systems. Additionally, it decreased the output voltage's THD and the voltage stress across the switches. The primary benefit is the capacitor's built-in capacity to balance voltage without the need for extra circuitry. Additionally, it has made the modulation algorithm simpler.
Claims:
The proposed topology has been optimized in this paper for utilizing a minimum number of switches, diodes, capacitors and voltage sources.
It generates nine-level output with a lesser number of components, inherent capability of the self-balance Voltage without using any external circuits,
NEWLY PROPOSED NINE-LEVEL CIRCUIT:
Circuit configuration:
Figure 1 depicts the setup of the suggested nine-level PWM inverter. It is made up of the main circuit and the auxiliary circuit. Four power switches and a single H-Bridge circuit make up the main circuit. It aids in the polarity shift of the output voltage. Five power switches, two diodes, two capacitors, and a single voltage source comprise the unique switching device combination that makes up the auxiliary circuit. It is in charge of creating the nine-level staircase output voltage by synthesizing the output voltage waveform. The output levels that the dc source Vdc can provide are 0, ±Vdc/2, ±Vdc, ±3Vdc/2, and ±2Vdc.

Cycles of operations:
The green and blue colors in Figures 2-10 represent a conductive route loop. To make the analysis easier, the following assumptions have been made: i) parasitic parameters are not taken into account, and ii) the switches and capacitors are to be regarded as ideal components. Table 1 displays the states that have been switched.
Here, "I" denotes that the switches and capacitors (C1, C2) are in the on position, "O" denotes that the switches are off, "D" denotes that the capacitors are being discharged, "C" denotes that the capacitors are being charged, and "-" denotes that the capacitors are being uncharged.
Level 0: A condition that can result in a 0 level is depicted in Figure 2. The SW2 and SW4 switches are activated, while the remaining switches are deactivated.
Level Vdc/2: A situation capable of producing a Vdc/2 Level is depicted in Figure 3. We are turning on the SW1, SW4, SW8, and SW9 switches. Two routes are used for the discharge of capacitors C1 and C2 to the load. The discharge of capacitor C1 occurs through SW1, SW4, SW8, and SW9, while the discharge of capacitor C2 occurs through D1, SW1, SW4, and SW8.
Level Vdc: A state capable of producing a (Vdc) level is depicted in Figure 4. The SW1, SW4, and SW5 switches are all in the active position. The load is receiving Vdc discharges through SW1, SW4, SW5, and D2.
Level 3Vdc/2: A state capable of producing a 3Vdc/2 Level is depicted in Figure 5. We are turning on the SW1, SW4, SW6, and SW9 switches. Both capacitors C1 and C2 are discharged with two routes; capacitor C1 discharges Vdc to the load through SW1, SW4, SW6, SW9, and capacitor C2 discharges Vdc to the load through SW1, SW4, SW6, and D1.

Level 2Vdc: A state capable of producing a 2Vdc level is depicted in Figure 6. We are turning on the SW1, SW4, SW6, and SW7 switches. Through SW1, SW4, SW6, and SW7, capacitors C1 and C2 in series with Vdc are discharged to the load.

Level -Vdc/2: A situation capable of producing a -Vdc/2 Level is depicted in Figure 7. We are turning on the SW2, SW3, SW8, and SW9 switches. Two pathways are used to discharge capacitors C1 and C2 to the load: capacitor C1 discharges through SW2, SW3, SW8, and SW9, while capacitor C2 discharges through D1, SW2, SW3, and SW8.

Level -Vdc: A condition that can result in a -Vdc Level is depicted in Figure 8. Vdc is being discharged to the load through SW2, SW3, SW5, and D2 as the switches SW2, SW3, and SW5 are being activated.

Level -3Vdc/2: A situation capable of producing a -3Vdc/2 Level is depicted in Figure 9. We are turning on the SW2, SW3, SW6, and SW9 switches. Capacitors C1 and C2 are two-path discharges. Capacitor C1 discharges to the load through SW2, SW3, SW6, SW9, and capacitor C2 discharges to the load through SW2, SW3, SW6, and D1 when connected in series with a dc source (Vdc).

Level -2Vdc: A situation capable of producing a -2Vdc level is depicted in Figure 10. Capacitors C1 and C2 in series with Vdc are discharged to the load through SW2, SW3, SW6, and SW7 while switches SW2, SW3, SW6, and SW7 are activated.

Analysis of modulation:
Figure 11 illustrates the suggested inverter system's working concept. The four quasi square waveforms 𝑣𝑜𝑗 (j=1, 2, 3, 4) make up the output voltage waveform (staircase structure) of the suggested system. Its conducting angle is α𝑗, and its magnitude is ±Vdc/2. In this case, the conducting angle needs to meet the requirement stated in (1).
0<α_1<α_2<α_3<α_4<α_5=〖90〗^0 (1)
The Fourier series representation for every quasi (square) waveform is (2).

v_oj=(2V_dc)/π ∑_(n=1,3,…)^∞▒cos⁡nα/n×sin⁡nωt (2)

In this case, the angular frequency is represented by ω. As a result, (3) is the output voltage Fourier decomposition.
v_oj=(2V_dc)/π ∑_(n=1,3,…)^∞▒∑_(j=1)^4▒cos⁡nαj/n×sin⁡nωt (3)

The output voltage waveform's basic component can be expressed as (4).

v_oj=(2V_dc)/π ∑_(j=1)^4▒cos⁡〖α_j 〗 ×sin⁡nωt (4)

For the fundamental components, the modulation index magnitude is 𝑀𝑜𝑖. One can compute the total harmonic distortion (THD) using equation (6).

M_oi=1/4 ∑_(j=1)^4▒cos⁡〖α_j 〗 (5)
THD=√(∑_(n=3,5….)^∞▒[∑_(j=1)^4▒(cos⁡n α_j)/n]^2 )/(∑_(n=1)^4▒cos⁡〖α_n 〗 )×100% (6)

The suggested system has been modulated using a chosen harmonic elimination technique. For the purpose of eliminating harmonics, the fifth, seventh, and eleventh components have been chosen. Here, can be used to calculate the conducting angles α𝑗.

cos⁡(α_1 )+cos⁡(α_2 )+cos⁡(α_3 )+cos⁡(α_4 )=4M_oi
cos⁡(〖5α〗_1 )+cos⁡(5α_2 )+cos⁡(〖5α〗_3 )+cos⁡(5α_4 )=0
cos⁡(〖7α〗_1 )+cos⁡(〖7α〗_2 )+cos⁡(〖7α〗_3 )+cos⁡(〖7α〗_4 )=0 (7) cos⁡(11α_1 )+cos⁡(〖11α〗_2 )+cos⁡(〖11α〗_3 )+cos⁡(〖11α〗_4 )=0
The conducting angles α𝑗 are determined in (8) using the preceding equation when the modulation index magnitude 𝑀𝑜𝑖 is set to 0.8.
α_1=〖10.28〗^0,α_2=〖21.16〗^0,α_3=〖40.36〗^0,α_4=〖61.06〗^0 (8)

Based on equations (6) and (8), the theoretical THD value of the nine-level multilevel inverter systems that are being described is 3.12%.



CALCULATING CAPACITORS AND ANALYZING LOSSES:
Analysis of ripple loss and computation of capacitors:
The capacitors will be affected by the voltage ripple. 10% of the capacitor's self-maximum voltage should be the maximum amount that can be discharged to the load. During the capacitors' discharge cycle, the voltage fluctuations can be identified. Table 1 and Figure 11 are visible. In the positive half-cycle, when producing output voltage levels of 3Vdc/2 and 2Vdc, the maximum continuous discharging period of both capacitors is equal between α3 and π-α3; in the negative half-cycle, the same discharging periods are obtained when producing output voltage levels of -3Vdc/2 and -2Vdc. The aforementioned Figures 2 to10 display the present path relations. Now, each capacitor's continuous discharge duration between α3 and π-α3 is as follows (9).
∆Q=∫_(α_3)^(α_4)▒〖io/2w dw+∫_(α_4)^(π-α_4)▒〖io/2w dwt+∫_(π-α_4)^(π-α_3)▒〖io/2w dwt〗〗〗 (9)
Here, the greatest discharge period and maximum voltage ripple for two capacitors are found under conditions of pure resistive load. The simulation waveform generates the staircase output voltage. The voltage ripple of the capacitor can therefore be calculated as (10).
∆V=V_dc/(4πfR_l c) (4π-3α_3-5α_4 ) (10)
Here, C is the capacitance value of both capacitors, f is the output waveform frequency, and 𝑅𝑙 is the output load resistance. (11) Can be used to calculate the minimal capacitance while accounting for the allowable voltage ripple.
C_min=V_dc/(4πfR_l c) (4π-3α_3-5α_4 ) (11)
The curve of the minimum capacitance against the output load and the minimum capacitance against the output frequency is displayed in Figures 12 and 13. Here, we discovered that the capacitance value should decrease as the frequency and resistance rise in order to keep the ripple voltage within a reasonable range. It confirms that the higher frequency can lower the capacitance value. Now, (12) can be used to calculate the ripple loss.
P_ripple=fC(∆V^2) (12)

CONCLUSION

Based on the innovative switching method, this research proposes a novel nine level inverter structure. This study optimizes the suggested topology to use the fewest possible switches, diodes, capacitors, and voltage sources. A comparison between this system and the newly suggested systems has been conducted. With fewer components and an innate ability to self-balance, it produces nine levels of output. The benefit of avoiding the voltage imbalance issue by utilizing no external circuits is that the system's complexity and cost are reduced. Additionally, it might make modulation circuits or algorithms simpler. The calculated total harmonic distortion (THD) value is a theoritically extremely low 3.12%. Additionally, it displays how best to distribute power loss among the switches. As a result, this system is more efficient. A simulation model with different loads, such as resistive, inductive, and motor, is used to evaluate the viability and advantages of the suggested system. , Claims:1. The proposed topology has been optimized in this paper for utilizing a minimum number of switches, diodes, capacitors and voltage sources.
2. It generates nine-level output with a lesser number of components, inherent capability of the self-balance Voltage without using any external circuits.

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