COMPARATIVE ANALYSIS OF POWER CONSUMPTION AND TRANSISTOR CURRENT FOR 6T AND 9T SRAM

Abstract

ABSTRACT The present invention relates in the field of electronics and more particularly on energy efficiency and the differences in transistor current flow and power consumption between 6T and 9T SRAM cells. With an emphasis on energy efficiency, it assesses both transient and DC power usage during read and write operations. In order to gain insights into reliability and performance, transistor current flow during these processes is also measured. The results help to optimize memory architectures for performance and energy economy.

Specification

Description:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Comparative Analysis of Power Consumption and Transistor Current for 6T And 9T SRAM




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

Comparative Analysis of Power Consumption and Transistor Current for 6T And 9T SRAM

Field of Invention:
The present invention relates in the field of electronics and more particularly on energy efficiency and determining the differences in transistor current flow and power consumption between 6T and 9T SRAM cells.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
A 6T SRAM unit is a kind of memory which stores information of one bit. Each bit is stored using a bistable latching circuitry. The main difference when compared with the dynamic RAM is that it does not require periodical restoring. Static RAM shows dataremanence property, but if the memory is not supplied with power the data will be lost. Whereas, 9T SRAM has 6T Static RAM architecture with 3 extra transistors. The three extra transistors are used for bypassing the read current from node referred as data storage. Upper sub circuit of 9T SRAM architecture forms the 6T SRAM cell. Transistors that are used to access bit lines and for read access forms lower sub circuit. Upper memory sub circuit is for the application of storing data. Data stored within the Static RAM cell controls the functioning of the cell. Write signal is used for controlling the transistors used for write access.
Currently, the device structures of 90 nm implementations of the 6T and 9T SRAM architectures are analyzed, with particular attention to power consumption during DC and transient activities. Energy efficiency requires an understanding of power dynamics during read and write operations. Additionally, the transistor current flow during SRAM operations, offering valuable insights into performance factors including speed and stability.

Therefore, there is need for analytical approach to examine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells and improving memory systems' energy economy and performance to optimize memory architectures for performance and energy economy/efficiency.
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide analytical approach to determine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells in read and write operations during transient and DC power usage both to optimize memory architectures for performance and energy economy/efficiency.

Summary of the Invention:
In an embodiment, the present invention provides a system and method to analyze and determine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells in read and write operations during transient and DC power usage both to optimize memory architectures for performance and energy economy/efficiency.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates Schematic of 6T SRAM.
Figure 2: illustrates Schematic of 9T SRAM
Figure 3: illustrates DC analysis of 6T SRAM.
Figure 4: illustrates DC analysis of 9T SRAM.
Figure 5: illustrates Transient power analysis of 6T SRAM.
Figure 6: illustrates Transient power analysis of 9T SRAM.
Figure 7: illustrates DC power response of 6T SRAM.
Figure 8: illustrates DC power response of 9T SRAM.
Figure 9: illustrates Transient analysis of Read operation (6T).
Figure 10: illustrates Transient analysis of Write operation (6T).
Figure 11: illustrates DC analysis of Read Operation (6T)
Figure 12: illustrates DC analysis of Write Operation (6T).
Figure 13: illustrates Transient analysis of Read operation (9T).
Figure 14: illustrates Transient analysis of Write operation (9T).
Figure 15: illustrates DC analysis of Read Operation (9T)
Figure 16: illustrates DC analysis of Write Operation (9T).

Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides an analytical approach to determine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells in read and write operations during transient and DC power usage both to optimize memory architectures for performance and energy economy/efficiency.

In another embodiment, the present invention provides a system to determine a approach to optimize memory architectures for performance and energy economy/efficiency.

Data manipulation is made possible by two cross-coupled inverters and access transistors in a traditional 6T SRAM (figure 1), which functions in read, write, and hold modes. When writing, the word line (WL) is active and data together with its complement are driven into bit lines (BL and BLB). Pre-charged bit lines move from a fixed to a floating state during reading, then one is raised while the other is kept HIGH to retrieve data. Efficiency depends on the cell ratio, which shows the aspect ratio of the drive to access transistors. The Q and QB pins of a typical IC memory block link to a sense amplifier in order to retrieve data. On the other hand, three more transistors in a 9T SRAM cell strengthen the pull-down action during reading, improving read access (see figure 2). For symmetry, the read and pull-down transistors' aspect ratios match the drive-NMOS. Differential pull-down improves read performance by lowering resistance between storage nodes and the ground when the read word line (RWL) is active. Disabled RWL reduces leakage current, increases efficiency and reliability.
In an embodiment figure 3, explains the Q and QBAR in a 6T SRAM, which are complimentary outputs that preserve logic values when subjected to static DC analysis. At Vin = 1.8V, access transistors turn on. DC analysis looks at steady-state node voltages in a 9T SRAM during read, write, and hold operations (see figure 4). Based on stored data and bit line voltages, Q and QBAR stable at distinct voltages. Precharged during reads and stored data have an impact on the BL and BLBAR voltages, which are then adjusted for writing new data. While RWL isolates the cell to provide correct separation during reads or writes, WL chooses the cell.
Power response for transient analysis
On performing the transient analysis of 6T SRAM with stimuli where WL is given a dc voltage of 1 V, voltage 1 = HIGH, and voltage 2 = LOW with time period of 20 ns and pulse width of 10 ns whereas BL and BLB complement each other in terms of voltage1 and voltage 2 with same time period and pulse width of 10 ns and 5 ns respectively [8]-[10]. This leads to analysis of SRAM for every possible combination. The figure 5 shown depicts the power consumption by the cell at every instant of time where the leakage power and read/write power are measured by drawing steady state current of the circuit for specific voltage and temperature, and by drawing the difference in current during read and write operations, respectively. As per the observation from the figure the peak power consumed during the power analysis ranges from (2×10-4 - 2.25×10-4) pW for read/write operations and for leakage power peak value ranges up to 2.45×10-5 pW.

A transient study of 9T SRAM is carried out by varying the stimuli and adding RWL as an additional input to increase the efficiency of the circuit [11]. Every parameter has a DC voltage of 1 V. The WL and RWL operate for 20 ns with a pulse width of 10 ns, and the voltages for both are complementary. The time interval for BL and BLB is 10 ns, the pulse width is 5 ns, and voltages 1 and 2 are complementary. Figure 6 illustrates that while a nearly flat line suggests the possibility of a stable state, there may be little oscillations. The simulation illustrates both the power consumption for read/write operations, with a peak value in the range of (2×10-4-2.25×10-4) pW, and leakage power, with a peak value of up to 8.7×10-5 pW.
On comparing the analysis of both circuits, the increase in leakage power can be observed as there is a rise in leakage current through the transistor, which provides a faster response to the circuit.
Power response for DC analysis
To analyze the power response of 6T and 9T SARM, we attach a variable dc source at Q to change the values continuously at one end of the circuit and scrutinize the value at another end. In order to realize the power consumption, we vary the voltage at Q from 0V to 1.8V, and the stimuli are identical to the transient one. The power calculated in the graph is the total power consumed in the circuit rather than instantaneous power or power at the transistor.

In case of 6T SRAM, as shown in figure 7, the power rises to 1.8×10-4 pW at initial point from -0.2 V to 2.0 V, and for 0.2 V to 0.4 V, we observe a rapid decrease in the power to 1.35×10-4 Pw and second and third peak occur in the range of 0.4V to 0.8V and 0.8V to 1.2V with power 1.63×10-4 pW and 1.75×10-4 pW respectively. The optimal range to operate, considering power consumption as a parameter, lies between 0.4 V and 0.8 V.

9T SRAM shows a totally different response for power analysis. Figure 8 shows a positive correlation between voltage and power, i.e., with an increase in applied voltage, the power consumption of the circuit increases. Initially, a dip is observed in the range of 0 V to 0.2 V with a peak power of 1.72×10-4 pW occurring at 0.58 V, followed by a gradual declination in power with an increase in voltage from 0.6 V to 1.8 V up to 0.7×10-4 pW. As we know, power consumption in CMOS is P = CV2, where P is power, C is capacitance, and V is voltage; the leakage current through the transistors increases with an increase in voltage, leading to higher power consumption.
CURRENT FLOW THROUGH TRANSISTOR IN 6T SRAM
Read and write operation in transient analysis
The current via the NMOS transistors is picoamp-level. This is how a 6T SRAM cell normally operates when the word line (WL) is LOW. The bit line (BL) and bit line bar (BLB) start out with HIGH voltages of approximately 0.99V. This implies that the cell is most likely storing a logic 1 value. The word line (WL) rises for a brief 2 ns period. This could indicate that a read or write activity. The stimuli is same as previous analysis in transient mode. Over the course of the read or write operation, the current passing through the NMOS transistors grows slightly. This is what happens when the transistors are turned on, allowing current to flow between the bit line and bit line bar. When the read or write operation is complete, the current flowing through the NMOS transistors returns to low levels, and the voltage at the bit line and bit line bar returns to its initial values. For write operation, WL is constantly kept HIGH and current for different BL and BLB combinations. We trace the current via NMOS (0) and NMOS (2). For read, BL and BLB are precharged first, and when WL gets logic high, they are discharged, and current is detected for figure 9 and figure 10.
Read and write operations in DC analysis
In DC analysis of current flow through 6T SRAM, we use the same stimuli, but we vary the voltage at Q or, say, BL, and BLB is kept ground to observe the change in current. As an output, we observe there is an increase in current in NMOS (0) and a dip for NMOS (2) up to 0.6 V, and after that, there is a sudden increase in current for NMOS (2) nearly about -0.2×10-4 pA whereas the current through NMOS (0) is saturated after 0.6 V. Figure 11 shows the behavior of transistors on varying values through them. In the specific graph we see, it appears that the drain current increases as the drain-to-source voltage increases for both NMOS (0) and NMOS (2). This indicates that the transistors are operating in the saturation region. The Wider channel will allow large currents to flow. For a write operation, shown in figure 12, WL is kept HIGH constantly, and we vary the voltage in the same manner, and the current through the transistor NMOS (0) is between -1.48×10-4 pA to 0 pA in the range 0 V to 1 V and after that current rise up to 5×10-5 pA, which signifies the change in direction of flow of electrons after 1V. Whereas for NMOS (2), current initially decreases to -7.48×10-5 pA from 0 V to 0.4 V and then a gradual increase in current after from 0.6 V to 1.8 V.
CURRENT FLOW THROUGH TRANSISTOR IN 9T SRAM
Read and write operations in transient analysis
Figure 13 shows the transient analysis of the read operation of a 9T SRAM cell. The current flowing through a few transistors is shown in picoamps at the bottom of the graph. For around five nanoseconds, the word line (WL) signal rises and stays HIGH. Because the access transistor has been engaged, the read word line (RWL) signal can now affect the output. The RWL signal rises at about 5 ns and stays HIGH for the duration of the simulation. The read path transistors are turned on, which precharges the bit line (BL) and bit line bar (BLB). When the RWL signal becomes HIGH, the BL node's voltage rises from 0V to roughly 1.2V. This implies that when the read operation is carried out, the transistor is responsible for bringing up the BL node. The time period and pulse width are the same as in previous cases. Only RWL is added that runs opposite to WL. The RWL signal rises HIGH when a 0 is read from the cell, meaning that the BL node is precharged to VDD and then discharged to a lower voltage level. Only a short period of time is shown by the transient reaction on the graph. The current flow of the other transistors in the circuit is not visible.
Additionally, figure shows the momentary reaction of a 9T SRAM cell during a write operation. At the outset, the Write Line (WL) becomes active, allowing access to the cell. The data to be written is received simultaneously by the Bit Line (BL) and its counterpart (BLB). On the storage node QBAR that is holding the complement, we can see a voltage transition. A successful write is indicated when the voltage on the BLB is effectively mirrored by the QBAR voltage as the write operation proceeds. This transition occurs in a brief period of time, around 5.2×10-8 seconds. A successful write cycle in the 9T SRAM cell is confirmed by the analysis, which points to effective data transfer from the bit lines to the storage node.
Read and write operations in DC analysis
In dc analysis of 9T SRAM for current flow in transistor simulation is performed with similar identical and voltage running source is also attached. During read operation, there is a gradual decrease in current or negative current up to 0.5V and negative peak value of 0.1×10-3 pA and then a rise to positive current with a maximum current of 0.98×10-4 pA. Then transistor current attains saturation until the next operation cycle for both NMOS (0) and NMOS (6). It appears that the current through the device increases exponentially as the voltage increases. The specific shape of the curve, shown in figure 15, depends on the particular NMOS device and its operating conditions. For the write operation shown in figure 16, NMOS (0) faces a declination in the current flow till 0.6V and then an inclination to max current of 0.49×10-4 pA whereas for NMOS (6), there is a constant increase in current from 0.165×10-3 pA to 0.5×10-4 pA. The graph appears to show that the current starts to increase rapidly at around 0.2 volts. This is known as the threshold voltage of the NMOS device.

CONCLUSION
Comparison of 6T and 9T SRAM cells provides interesting insights into their power responses and operational characteristics. Both exhibit their maximum power usage during read/write operations when subjected to transient analysis. Nevertheless, while 9T SRAM has a greater leakage current, which enhances circuit responsiveness, it exhibits higher leakage power. However, DC analysis shows a considerable difference in behavior. The best operating range of 6T SRAM is between 0.4V and 0.8V. This is in contrast to 9T SRAM, which shows a linear relationship between voltage and power consumption because of an increase in leakage current with higher voltage. Moreover, the DC study of current flow via transistors reveals distinct trends during read and write operations for both SRAM types. Unlike 6T SRAM, which displays varying current behaviors with voltage changes, 9T SRAM emphasizes variances in transistor behavior by presenting exponential climbs in current throughout both read and write operations. All things considered, these findings demonstrate how crucial circuit design choices are in dictating operational efficacy and power consumption, offering useful knowledge for optimizing SRAM performance in a variety of applications. A greater voltage is desired because lowering it will cause operations to operate slowly, but doing so will result in an increase in power consumption. Thus, there is a trade-off between power consumption and performance.
, Claims:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Comparative Analysis of Power Consumption and Transistor Current for 6T And 9T SRAM




APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

Comparative Analysis of Power Consumption and Transistor Current for 6T And 9T SRAM

Field of Invention:
The present invention relates in the field of electronics and more particularly on energy efficiency and determining the differences in transistor current flow and power consumption between 6T and 9T SRAM cells.

Background of the Invention.
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
A 6T SRAM unit is a kind of memory which stores information of one bit. Each bit is stored using a bistable latching circuitry. The main difference when compared with the dynamic RAM is that it does not require periodical restoring. Static RAM shows dataremanence property, but if the memory is not supplied with power the data will be lost. Whereas, 9T SRAM has 6T Static RAM architecture with 3 extra transistors. The three extra transistors are used for bypassing the read current from node referred as data storage. Upper sub circuit of 9T SRAM architecture forms the 6T SRAM cell. Transistors that are used to access bit lines and for read access forms lower sub circuit. Upper memory sub circuit is for the application of storing data. Data stored within the Static RAM cell controls the functioning of the cell. Write signal is used for controlling the transistors used for write access.
Currently, the device structures of 90 nm implementations of the 6T and 9T SRAM architectures are analyzed, with particular attention to power consumption during DC and transient activities. Energy efficiency requires an understanding of power dynamics during read and write operations. Additionally, the transistor current flow during SRAM operations, offering valuable insights into performance factors including speed and stability.

Therefore, there is need for analytical approach to examine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells and improving memory systems' energy economy and performance to optimize memory architectures for performance and energy economy/efficiency.
Object(s) of the present invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An object of the present invention is to provide analytical approach to determine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells in read and write operations during transient and DC power usage both to optimize memory architectures for performance and energy economy/efficiency.

Summary of the Invention:
In an embodiment, the present invention provides a system and method to analyze and determine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells in read and write operations during transient and DC power usage both to optimize memory architectures for performance and energy economy/efficiency.

Brief description of Drawings:
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. The reference numbers are used throughout the figures to describe the features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which
Figure 1: illustrates Schematic of 6T SRAM.
Figure 2: illustrates Schematic of 9T SRAM
Figure 3: illustrates DC analysis of 6T SRAM.
Figure 4: illustrates DC analysis of 9T SRAM.
Figure 5: illustrates Transient power analysis of 6T SRAM.
Figure 6: illustrates Transient power analysis of 9T SRAM.
Figure 7: illustrates DC power response of 6T SRAM.
Figure 8: illustrates DC power response of 9T SRAM.
Figure 9: illustrates Transient analysis of Read operation (6T).
Figure 10: illustrates Transient analysis of Write operation (6T).
Figure 11: illustrates DC analysis of Read Operation (6T)
Figure 12: illustrates DC analysis of Write Operation (6T).
Figure 13: illustrates Transient analysis of Read operation (9T).
Figure 14: illustrates Transient analysis of Write operation (9T).
Figure 15: illustrates DC analysis of Read Operation (9T)
Figure 16: illustrates DC analysis of Write Operation (9T).

Detailed description of the invention:
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example, in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.
The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
In an embodiment, the present invention provides an analytical approach to determine the differences in transistor current flow and power consumption between 6T and 9T SRAM cells in read and write operations during transient and DC power usage both to optimize memory architectures for performance and energy economy/efficiency.

In another embodiment, the present invention provides a system to determine a approach to optimize memory architectures for performance and energy economy/efficiency.

Data manipulation is made possible by two cross-coupled inverters and access transistors in a traditional 6T SRAM (figure 1), which functions in read, write, and hold modes. When writing, the word line (WL) is active and data together with its complement are driven into bit lines (BL and BLB). Pre-charged bit lines move from a fixed to a floating state during reading, then one is raised while the other is kept HIGH to retrieve data. Efficiency depends on the cell ratio, which shows the aspect ratio of the drive to access transistors. The Q and QB pins of a typical IC memory block link to a sense amplifier in order to retrieve data. On the other hand, three more transistors in a 9T SRAM cell strengthen the pull-down action during reading, improving read access (see figure 2). For symmetry, the read and pull-down transistors' aspect ratios match the drive-NMOS. Differential pull-down improves read performance by lowering resistance between storage nodes and the ground when the read word line (RWL) is active. Disabled RWL reduces leakage current, increases efficiency and reliability.
In an embodiment figure 3, explains the Q and QBAR in a 6T SRAM, which are complimentary outputs that preserve logic values when subjected to static DC analysis. At Vin = 1.8V, access transistors turn on. DC analysis looks at steady-state node voltages in a 9T SRAM during read, write, and hold operations (see figure 4). Based on stored data and bit line voltages, Q and QBAR stable at distinct voltages. Precharged during reads and stored data have an impact on the BL and BLBAR voltages, which are then adjusted for writing new data. While RWL isolates the cell to provide correct separation during reads or writes, WL chooses the cell.
Power response for transient analysis
On performing the transient analysis of 6T SRAM with stimuli where WL is given a dc voltage of 1 V, voltage 1 = HIGH, and voltage 2 = LOW with time period of 20 ns and pulse width of 10 ns whereas BL and BLB complement each other in terms of voltage1 and voltage 2 with same time period and pulse width of 10 ns and 5 ns respectively [8]-[10]. This leads to analysis of SRAM for every possible combination. The figure 5 shown depicts the power consumption by the cell at every instant of time where the leakage power and read/write power are measured by drawing steady state current of the circuit for specific voltage and temperature, and by drawing the difference in current during read and write operations, respectively. As per the observation from the figure the peak power consumed during the power analysis ranges from (2×10-4 - 2.25×10-4) pW for read/write operations and for leakage power peak value ranges up to 2.45×10-5 pW.

A transient study of 9T SRAM is carried out by varying the stimuli and adding RWL as an additional input to increase the efficiency of the circuit [11]. Every parameter has a DC voltage of 1 V. The WL and RWL operate for 20 ns with a pulse width of 10 ns, and the voltages for both are complementary. The time interval for BL and BLB is 10 ns, the pulse width is 5 ns, and voltages 1 and 2 are complementary. Figure 6 illustrates that while a nearly flat line suggests the possibility of a stable state, there may be little oscillations. The simulation illustrates both the power consumption for read/write operations, with a peak value in the range of (2×10-4-2.25×10-4) pW, and leakage power, with a peak value of up to 8.7×10-5 pW.
On comparing the analysis of both circuits, the increase in leakage power can be observed as there is a rise in leakage current through the transistor, which provides a faster response to the circuit.
Power response for DC analysis
To analyze the power response of 6T and 9T SARM, we attach a variable dc source at Q to change the values continuously at one end of the circuit and scrutinize the value at another end. In order to realize the power consumption, we vary the voltage at Q from 0V to 1.8V, and the stimuli are identical to the transient one. The power calculated in the graph is the total power consumed in the circuit rather than instantaneous power or power at the transistor.

In case of 6T SRAM, as shown in figure 7, the power rises to 1.8×10-4 pW at initial point from -0.2 V to 2.0 V, and for 0.2 V to 0.4 V, we observe a rapid decrease in the power to 1.35×10-4 Pw and second and third peak occur in the range of 0.4V to 0.8V and 0.8V to 1.2V with power 1.63×10-4 pW and 1.75×10-4 pW respectively. The optimal range to operate, considering power consumption as a parameter, lies between 0.4 V and 0.8 V.

9T SRAM shows a totally different response for power analysis. Figure 8 shows a positive correlation between voltage and power, i.e., with an increase in applied voltage, the power consumption of the circuit increases. Initially, a dip is observed in the range of 0 V to 0.2 V with a peak power of 1.72×10-4 pW occurring at 0.58 V, followed by a gradual declination in power with an increase in voltage from 0.6 V to 1.8 V up to 0.7×10-4 pW. As we know, power consumption in CMOS is P = CV2, where P is power, C is capacitance, and V is voltage; the leakage current through the transistors increases with an increase in voltage, leading to higher power consumption.
CURRENT FLOW THROUGH TRANSISTOR IN 6T SRAM
Read and write operation in transient analysis
The current via the NMOS transistors is picoamp-level. This is how a 6T SRAM cell normally operates when the word line (WL) is LOW. The bit line (BL) and bit line bar (BLB) start out with HIGH voltages of approximately 0.99V. This implies that the cell is most likely storing a logic 1 value. The word line (WL) rises for a brief 2 ns period. This could indicate that a read or write activity. The stimuli is same as previous analysis in transient mode. Over the course of the read or write operation, the current passing through the NMOS transistors grows slightly. This is what happens when the transistors are turned on, allowing current to flow between the bit line and bit line bar. When the read or write operation is complete, the current flowing through the NMOS transistors returns to low levels, and the voltage at the bit line and bit line bar returns to its initial values. For write operation, WL is constantly kept HIGH and current for different BL and BLB combinations. We trace the current via NMOS (0) and NMOS (2). For read, BL and BLB are precharged first, and when WL gets logic high, they are discharged, and current is detected for figure 9 and figure 10.
Read and write operations in DC analysis
In DC analysis of current flow through 6T SRAM, we use the same stimuli, but we vary the voltage at Q or, say, BL, and BLB is kept ground to observe the change in current. As an output, we observe there is an increase in current in NMOS (0) and a dip for NMOS (2) up to 0.6 V, and after that, there is a sudden increase in current for NMOS (2) nearly about -0.2×10-4 pA whereas the current through NMOS (0) is saturated after 0.6 V. Figure 11 shows the behavior of transistors on varying values through them. In the specific graph we see, it appears that the drain current increases as the drain-to-source voltage increases for both NMOS (0) and NMOS (2). This indicates that the transistors are operating in the saturation region. The Wider channel will allow large currents to flow. For a write operation, shown in figure 12, WL is kept HIGH constantly, and we vary the voltage in the same manner, and the current through the transistor NMOS (0) is between -1.48×10-4 pA to 0 pA in the range 0 V to 1 V and after that current rise up to 5×10-5 pA, which signifies the change in direction of flow of electrons after 1V. Whereas for NMOS (2), current initially decreases to -7.48×10-5 pA from 0 V to 0.4 V and then a gradual increase in current after from 0.6 V to 1.8 V.
CURRENT FLOW THROUGH TRANSISTOR IN 9T SRAM
Read and write operations in transient analysis
Figure 13 shows the transient analysis of the read operation of a 9T SRAM cell. The current flowing through a few transistors is shown in picoamps at the bottom of the graph. For around five nanoseconds, the word line (WL) signal rises and stays HIGH. Because the access transistor has been engaged, the read word line (RWL) signal can now affect the output. The RWL signal rises at about 5 ns and stays HIGH for the duration of the simulation. The read path transistors are turned on, which precharges the bit line (BL) and bit line bar (BLB). When the RWL signal becomes HIGH, the BL node's voltage rises from 0V to roughly 1.2V. This implies that when the read operation is carried out, the transistor is responsible for bringing up the BL node. The time period and pulse width are the same as in previous cases. Only RWL is added that runs opposite to WL. The RWL signal rises HIGH when a 0 is read from the cell, meaning that the BL node is precharged to VDD and then discharged to a lower voltage level. Only a short period of time is shown by the transient reaction on the graph. The current flow of the other transistors in the circuit is not visible.
Additionally, figure shows the momentary reaction of a 9T SRAM cell during a write operation. At the outset, the Write Line (WL) becomes active, allowing access to the cell. The data to be written is received simultaneously by the Bit Line (BL) and its counterpart (BLB). On the storage node QBAR that is holding the complement, we can see a voltage transition. A successful write is indicated when the voltage on the BLB is effectively mirrored by the QBAR voltage as the write operation proceeds. This transition occurs in a brief period of time, around 5.2×10-8 seconds. A successful write cycle in the 9T SRAM cell is confirmed by the analysis, which points to effective data transfer from the bit lines to the storage node.
Read and write operations in DC analysis
In dc analysis of 9T SRAM for current flow in transistor simulation is performed with similar identical and voltage running source is also attached. During read operation, there is a gradual decrease in current or negative current up to 0.5V and negative peak value of 0.1×10-3 pA and then a rise to positive current with a maximum current of 0.98×10-4 pA. Then transistor current attains saturation until the next operation cycle for both NMOS (0) and NMOS (6). It appears that the current through the device increases exponentially as the voltage increases. The specific shape of the curve, shown in figure 15, depends on the particular NMOS device and its operating conditions. For the write operation shown in figure 16, NMOS (0) faces a declination in the current flow till 0.6V and then an inclination to max current of 0.49×10-4 pA whereas for NMOS (6), there is a constant increase in current from 0.165×10-3 pA to 0.5×10-4 pA. The graph appears to show that the current starts to increase rapidly at around 0.2 volts. This is known as the threshold voltage of the NMOS device.

CONCLUSION
Comparison of 6T and 9T SRAM cells provides interesting insights into their power responses and operational characteristics. Both exhibit their maximum power usage during read/write operations when subjected to transient analysis. Nevertheless, while 9T SRAM has a greater leakage current, which enhances circuit responsiveness, it exhibits higher leakage power. However, DC analysis shows a considerable difference in behavior. The best operating range of 6T SRAM is between 0.4V and 0.8V. This is in contrast to 9T SRAM, which shows a linear relationship between voltage and power consumption because of an increase in leakage current with higher voltage. Moreover, the DC study of current flow via transistors reveals distinct trends during read and write operations for both SRAM types. Unlike 6T SRAM, which displays varying current behaviors with voltage changes, 9T SRAM emphasizes variances in transistor behavior by presenting exponential climbs in current throughout both read and write operations. All things considered, these findings demonstrate how crucial circuit design choices are in dictating operational efficacy and power consumption, offering useful knowledge for optimizing SRAM performance in a variety of applications. A greater voltage is desired because lowering it will cause operations to operate slowly, but doing so will result in an increase in power consumption. Thus, there is a trade-off between power consumption and performance.

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