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Boosting Thermal Conductivity of GAA FET for future IC Applications

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Boosting Thermal Conductivity of GAA FET for future IC Applications

ORDINARY APPLICATION

Published

date

Filed on 16 November 2024

Abstract

Boosting the performance of Gate-All-Around (GAA) MOSFETs involves several key design considerations and strategies to improve their structure. The gate is covered to the channel through oxide materials to provide 360-degree control and isolation between metal and semiconductor. This configuration significantly enhances gate control over the channel, reducing leakage currents and improving subthreshold slope. High-k dielectrics and metal gates are often used to minimize gate leakage and enhance drive current. Novel material for the Channels can be designed as nanowires or nanosheets which provide excellent electrostatic control, thermal conductivity and nanosheets offer higher drive current due to their larger cross-sectional area.

Patent Information

Application ID202441088819
Invention FieldELECTRONICS
Date of Application16/11/2024
Publication Number47/2024

Inventors

NameAddressCountryNationality
Nithin Kumar N RDepartment of Electronics & Communication Engineering, Dayananda Sagar College of Engineering, Bangalore-560111IndiaIndia
Dr. Dinesha PDepartment of Electronics & Communication Engineering, Dayananda Sagar College of Engineering, Bangalore-560111IndiaIndia

Applicants

NameAddressCountryNationality
Dayananda Sagar College of EngineeringShavige Malleshwara Hills, Kumaraswamy Layout, BangaloreIndiaIndia

Specification

Description:FIELD OF INVENTION
[001] This invention is based on boosting the performance for the semiconductor devices which is beneficial to cater issues related to the design constraints.
BACKGROUND AND PRIOR ART
[002] With regard to integrated circuit (IC) design, the gate-all-around Field-effect Transistor (GAA FET) is a noteworthy invention, especially in consideration of developing semiconductor technology. Comparing GAA FETs to conventional planar and FinFET devices, the gate encircles the channel, providing greater oversight over the channel. The improved electrostatic control and decreased leakage current resulting from this improved control are essential for downsizing to smaller technological nodes.
[003] In GAA architectures, short-channel effects-which impair MOSFET performance at smaller scales-are reduced. These transistors are more effective for high-density integrated circuits (ICs) because to the gate's overall control, which also helps to maintain the threshold voltage and decrease off-state leakage. Because the GAA FETs can give higher channel control and lower leakage currents, they have better drive current and performance characteristics. Better switching rates and general performance in high-speed and low-power applications result from this. More design flexibility is possible with MOSFETs, particularly when creating three-dimensional structures. Their architecture offers the best possible balance between power consumption and performance, and it can be tailored for a variety of applications.
[004] New materials that can further improve transistor performance, such as high-mobility channels (germanium, III-V compounds), are compatible with the structure of GAA FETs. The development of next-generation integrated circuits (ICs), which need sophisticated materials for better performance, depends on this compatibility. The development of stacked transistor designs is made easier by GAA FET, and this can greatly improve IC performance and transistor density. This is especially useful for applications like system-on-chip (SoC) designs and three-dimensional integrated circuits (ICs) that call for high levels of miniaturisation and integration.
SUMMARY OF THE INVENTION
[005] A potential component for advanced circuit design is the GAA FET (101). The innovative geometric design of the GAA FET has improved its performance by substituting the traditional semiconductor channel material(202)-and the semiconductor channel is encircled by an oxide material that provides isolation between the device's gates-for the semiconductor material (201). To enhance the device's overall performance, two high K dielectric materials (203) & (204) are used in the stacked gate dielectric. The greater work function (205) of the metal gate will improve electrostatic control and add to the IC technology's design limitations.
DETAILED DESCRIPTION OF THE INVENTION
[006] Enhancing the efficiency of Gate-All-Around (GAA) MOSFETs through improved thermal conductivity necessitates some crucial design factors and structural enhancement techniques. To give metal and semiconductors complete isolation and 360-degree control, the gate is covered to the channel by oxide materials. This arrangement improves the subthreshold slope and reduces leakage currents while greatly enhancing gate control over the channel.
[007] Metal gates and high-k dielectrics are frequently utilized to reduce gate leakage and increase driving current. A unique shape for the semiconducting channel can be created using nanowires or nanosheets, which allow superior electrostatic control and better thermal conductivity. Because of their larger cross-sectional area, nanosheets can accommodate higher driving currents.
[008] Enhancing the efficiency of Gate-All-Around (GAA) MOSFETs through improved thermal conductivity necessitates many crucial design factors and material enhancement techniques. To give metal and semiconductors complete isolation and 360-degree control, the gate is covered to the channel by oxide materials. This arrangement improves the subthreshold slope and reduces leakage currents while greatly enhancing gate control over the channel.
[009] Metal gates and high-k dielectrics are frequently utilised to reduce gate leakage and increase driving current. A unique shape for the semiconducting channel can be created using nanowires or nanosheets, which allow superior electrostatic control. Because of their larger cross-sectional area, nanosheets can accommodate higher driving currents.
[010] The unique device is applied to cater for the issues faced by the classical devices. To compare the analysis with the classical device, input characteristics for digital applications are taken into account.
[011] The plot of transconductance, which establishes the sensitivity of the GAA device, is analysed using the same design. It gives the rate at which the output current varies about the supplied voltage.
[012] The three-dimensional GAA FET structure, in which a gate around the channel regulates the flow of electrons, serves as a representation of the analysis.
[013] Figure 2 depicts the device's two-dimensional structure, with the boron Arsenide as a semiconductor material. The semiconductor and the metal gate are encased in the layered dielectric layers. Higher permittivity dielectric materials enable improved scalability and performance at cutting-edge technology nodes that provide effective oxide thickness.
[014] Higher gate capacitance for the same physical thickness on the SiO2 counterpart is achieved by using high-k (high dielectric constant) materials such as silicon nitride (Si3N4) and hafnium dioxide (HfO2). This improves channel control and lowers leakage current.
Brief Description of the Drawings
[015] The disclosure will be described and explained with additional specificity and detail with accompanying figures in which Figure 1. depicts the 3D structure of the novel GAA device (101). Figure 2. represents the cross-sectional view of the novel semiconductor device incorporating the 2 stacked dielectric materials (203) & (204) surrounded by boron arsenide as a semiconductor channel (202), providing better thermal conductivity and electrostatic potential in turn the threshold voltage. The metal gate (205) with a higher work function is used to improve the transport mechanism of the electron flow. , C , Claims:1. A GAA FET (101) comprises a boron arsenide-based semiconducting channel (201) and stacked dielectric materials (202) and (203) with a metal gate of higher work function (204);
2. A GAA FET (101) as claimed in claim 1 wherein the boron arsenide material (201) provides a better electrostatic potential and thermal conductivity by isolating the effect of the gate;
3. A GAA FET (101) as claimed in claim 1 wherein the thin layer of semiconductor material (201) with higher doping concentration establishes better mobility through the gate bias;
4. A GAA FET (101) as claimed in claim 1 wherein the thin layer stacked dielectric materials (202) and (203) with higher permittivity increases the overall capacitance which provides better control over the semiconducting channel and increases the threshold voltage by 0.9 mV;
5. A GAA FET (101) as claimed in claim 1 wherein the metal gate (204) with the higher work function provides a high electric field across the semiconducting channel and higher drain current; and
6. A GAA FET (101) as claimed in claim 1, claim 4, and 5, wherein the change in threshold voltage of 0.9 mV and higher the drain current is suited for low-power digital circuit applications.

Documents

NameDate
202441088819-COMPLETE SPECIFICATION [16-11-2024(online)].pdf16/11/2024
202441088819-DRAWINGS [16-11-2024(online)].pdf16/11/2024
202441088819-FORM 1 [16-11-2024(online)].pdf16/11/2024
202441088819-FORM 18 [16-11-2024(online)].pdf16/11/2024
202441088819-FORM-9 [16-11-2024(online)].pdf16/11/2024
202441088819-REQUEST FOR EARLY PUBLICATION(FORM-9) [16-11-2024(online)].pdf16/11/2024
202441088819-REQUEST FOR EXAMINATION (FORM-18) [16-11-2024(online)].pdf16/11/2024

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