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Analyzing the performance of various Vedic multipliers designed for DSP architecture processors
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Abstract
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Analyzing the performance of various Vedic multipliers designed for DSP architecture processors
ORDINARY APPLICATION
Published
Filed on 2 April 2023
Patent Information
| Application ID | 202341025125 |
| Date of Application | 02/04/2023 |
Documents
| Name | Date |
|---|---|
| 202341025125-COMPLETE SPECIFICATION [02-04-2023(online)].pdf | 02/04/2023 |
| 202341025125-DECLARATION OF INVENTORSHIP (FORM 5) [02-04-2023(online)].pdf | 02/04/2023 |
| 202341025125-DRAWINGS [02-04-2023(online)].pdf | 02/04/2023 |
| 202341025125-FORM 1 [02-04-2023(online)].pdf | 02/04/2023 |
| 202341025125-FORM-9 [02-04-2023(online)].pdf | 02/04/2023 |
| 202341025125-REQUEST FOR EARLY PUBLICATION(FORM-9) [02-04-2023(online)].pdf | 02/04/2023 |
