ANALOG/RF PERFORMANCE ANALYSIS OF A NOVEL SI0.9GE0.1/INAS CHARGE PLASMA BASED JUNCTIONLESS TFET

Abstract

The primary objective of the present invention is to overcome the drawback associated with prior art. An objective of the present invention is to provide an Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET.

Specification

Description:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET



APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.


Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET

Field of Invention:
The present invention relates to an Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET.
Background of the Invention
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The primary operating mechanism of MOSFETs is?thermionic emission, which?causes a degradation in performance that includes significant leakage current and subthreshold slope values greater than 60 mV/decade. Numerous?traditional devices such as?heterojunction bipolar transistors (HBT), High Electron Mobility transistors (HEMT), Negative Capacitance FETs, and CMOS (a blend of nMOS and pMOS) look to be promising in some technical?difficulties but worsen in others. The continuous reduction in the size of CMOS technology over the former few ages has resulted in considerable improvements in form of fast speed and packing density, but fabricating very narrow junctions at nanoscale size becomes very difficult. Very-narrow junctions with a high level of doping can be created using various methods, including ion implantation and annealing, however, these suffer from random dopant luctuations (RDFs). In addition to these problems, MOSFET downscaling resulted in significant leakage current and static power dissipations.

The devices that solve the problems of greater leakage current, quick switching, and reduced subthreshold slope are Tunnel Field Effect Transistors. The TFET, a gated p-i-n device that is often reverse biased, is one example of such a device. Quantum mechanical Band-to-Band Tunneling (BTBT) causes the driving current in TFETs, which enables the device to have SS lower than 60 mV/decade. The fundamental advantage of TFETs is how easily they can be incorporated into the current CMOS architecture, enabling us to construct TFET-based devices using existing methods. As a result, TFETs have evolved into more and more intriguing transistor possibilities over time. Numerous research papers published in the last several decades have emphasized the significance of TFET, yet, achieving low ON-current and fabricating metallurgical connections has proven to be challenging. Junctionless TFETs have entered the scene to fulfill the demands of contemporary technologies. The benefits of both junctionless FETs and TFETs are combined in junctionless TFETs. In contrast to MOSFETs, junctionless FET exhibits high ON current and less fluctuation since it lacks a metallurgical junction. Low ON-current is a problem for TFETs, despite their higher SS. JLTFETs operate under the premise that charge plasma can induce source and drain areas.

Objective of the Invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An objective of the present invention is to provide an Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET.
Detailed description of drawings:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:

Fig. 1: Illustrate DEVICE STRUCTURE AND DIMENSIONS
Detailed description:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.

It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.

The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The present invention provides a charge plasma-based hetero structure?junctionless TFET using novel?coalescence?of Si1-xGex/InAs with HfO2 and SiO2 assembled at the gate terminal. Si1-xGex is employed in the source part, while InAs is incorporated in the channel and drain portions. In this paper, simulations are accomplished through the Silvaco-ATLAS software?to explore different device parameters. At standard temperature (300K), the characteristics of the suggested device, DMG-HJLTFET, are analyzed, and its analog/RF?performance is compared to that of traditional Si-JLTFET. The proposed device performs better than the existing ones according to all the criteria and traits.
The remaining segment of the invention is arranged in this way:?device description is discussed?in segment II, segment III examines simulation results, and?? Segment IV discusses important outcomes of the paper.
II. DEVICE STRUCTURE AND DIMENSIONS
Fig. 1 depicts the graphical outlook of (a) our suggested device, dual material?gate hetero-structure?junctionless TFET (DMG-HJLTFET), and (b) traditional homo-material Si-JLTFET. Both devices have a lateral n-type JLTFET architecture with a uniformly doped semiconductor body with a concentration of 1x10-19. DMG-HJLTFET and Si-JLTFET work on the charge plasma concept in which two gate is used, named polar gate (PG) and control gate (CG). PG is situated above the source and has a higher work function; on the other hand, CG is located above the channel and has a lower work function. The main objective of these gates is to convert an exceedingly doped n+-n+-n+ structure into a p+-i-n+ typical structure. Table I, lists the device's structural parameters. The control gates and the polar gate's respective work functions are 4.5 eV and 5.93 eV.
Both devices have a body thickness of 3 nm and a channel length of 20 nm. As dielectric materials, HfO2 and SiO2, 1 nm thickness of each are used in DMG-HJLTFET, whereas SiO2 of 2 nm breadth is applied as a dielectric material in Si-JLTFET. In order to isolate PG and CG, the gap width is kept at 2 nm. Both devices maintain the same doping concentration of 1x1019cm-3. To achieve the necessary polarity of the source, channel, and drain sections the charged plasma concept is incorporated, and the doping concentration is set to be consistent.
TABLE I. Parameters Incorporated in Simulated Structure

DMG-HJLTFET
Device Parameters Value Units
PG Length (LPG) 18 nm
CG Length (LCG) 20 nm
Body Thickness (TBODY) 3 nm
PG work function 5.93 eV
CG work function 4.5 eV
Gap among PG and CG (LSP) 2 nm
The SILVACO-ATLAS software is used for simulations . Non-local band-to-band tunneling model is incorporated because TFET utilizes the tunneling barrier to work on the band-to-band tunneling process. The electric field at each mesh node of the simulated architecture is unrelated to the non-local models. It depends on the device's band structure as well as the bands' spatial fluctuation. The Auger recombination model and band gap narrowing (BGN) are also used. The trap-assisted tunneling model is also applied to consider the impacts of traps. The SRH recombination model is adopted because of the high impurity concentration in the channel region. Additionally used are the CVT model (Lombardi) and Fermi-Dirac statistics. The parallel, perpendicular, temperature- and concentration-dependent electric field mobility are all included in the CVT model. The quantum confinement model proposed by Hansch is also enabled because the body thickness is 3 nm.
The suggested device is simulated and calibrated using the experimental values of a manufactured JLTFET?with a 20?nm gate length, and it also demonstrates the validity of the simulations and models used. The fabrication flow steps of the proposed device DMG-HJLTFET.

Analog and RF parameters of DMG-HJLTFET and Si-JLTFET are discussed in form of transfer characteristics (IDS-VGS), transconductance (gm), total parasitic capacitance (Cgg), maximum oscillation frequency (fmax), gain bandwidth product (GBP), transconductance frequency product (TFP), and Intrinsic Delay.
The parameters mentioned above are being analyzed by Eqn. 1 to Eqn. 6 as discussed below.
1. Transconductance:
gm=?IDS?VGS gm=??IDS??VGS
(1)
2. Total parasitic capacitance:

Cgg=Cgs+Cgd (2)Cgg=Cgs+Cgd (2)

3. Maximum oscillation frequency:

fmax=fT8p(RoutCgd)----------v (3) fmax=fT8??(RoutCgd) (3)

4. Gain bandwidth product:

GBP=gm20pCgd (4)GBP=gm20??Cgd (4)

5. Transconductance frequency product:

TFP=gmIDSXfT (5)TFP=gmIDSXfT (5)

6. Intrinsic delay:

t=CggXVddIDS (6)??=CggXVddIDS (6)

where IDS, VGS, Cgs, Cgd, fT, and Rout represents drain current, gate voltage, the gate to source capacitance, the gate to drain capacitance, cut-off frequency and output resistance respectively
The transfer characteristics of DMG-HJLTFET?and Si-?JLTFET. The use of hetero- material Si1-xGex/InAs?in the source/channel (SE/CL)?regions to implement bandgap engineering results in a wider tunneling barrier breadth?at the SE/CL?contact when no gate bias is applied. As a result, the barrier can only be tunneled by a small number of minority carriers, resulting in very low IOFF. The overlapping of the bands at the SE/CL?contact occurs when the gate voltage is applied?as a result, tunnel barrier width decreases. The ION now increases as more carriers have enough energy to tunnel through the SE/CL contact. Further use of dual dielectric material at the gate enhances the ION and minimizes the IOFF current, as a result, the ION current of DMG-HJLTFET is ~389 times greater in comparison to Si- JLTFET.
gm is a very crucial parameter concerning RF/wireless communications. It is the factor on which the amplification and efficiency of any system depend. For a more significant current conversion rate, gm should be high. The gm of DMG-HJLTFET is 10900% greater than Si-JLTFET, which shows the superiority of DMG-HJLTFET over Si-JLTFET in RF applications.
Fig. 6 shows the comparison of Cgg value among both devices. For smooth RF application, the Cgg value should be low. From the graph, it is clear that the DMG-HJLTFET Cgg value starts to decrease at higher gate voltage, whereas Cgg value of Si-JLTFET continuously increases for the entire gate voltage range.
, Claims:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)



Title: Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET



APPLICANT DETAILS:
(a) NAME: GRAPHIC ERA DEEMED TO BE UNIVERSITY
(b) NATIONALITY: Indian
(c) ADDRESS: 566/6, Bell Road, Society Area, Clement Town, Dehradun - 248002,
Uttarakhand, India







PREAMBLE TO THE DESCRIPTION:
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.


Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET

Field of Invention:
The present invention relates to an Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET.
Background of the Invention
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
The primary operating mechanism of MOSFETs is?thermionic emission, which?causes a degradation in performance that includes significant leakage current and subthreshold slope values greater than 60 mV/decade. Numerous?traditional devices such as?heterojunction bipolar transistors (HBT), High Electron Mobility transistors (HEMT), Negative Capacitance FETs, and CMOS (a blend of nMOS and pMOS) look to be promising in some technical?difficulties but worsen in others. The continuous reduction in the size of CMOS technology over the former few ages has resulted in considerable improvements in form of fast speed and packing density, but fabricating very narrow junctions at nanoscale size becomes very difficult. Very-narrow junctions with a high level of doping can be created using various methods, including ion implantation and annealing, however, these suffer from random dopant luctuations (RDFs). In addition to these problems, MOSFET downscaling resulted in significant leakage current and static power dissipations.

The devices that solve the problems of greater leakage current, quick switching, and reduced subthreshold slope are Tunnel Field Effect Transistors. The TFET, a gated p-i-n device that is often reverse biased, is one example of such a device. Quantum mechanical Band-to-Band Tunneling (BTBT) causes the driving current in TFETs, which enables the device to have SS lower than 60 mV/decade. The fundamental advantage of TFETs is how easily they can be incorporated into the current CMOS architecture, enabling us to construct TFET-based devices using existing methods. As a result, TFETs have evolved into more and more intriguing transistor possibilities over time. Numerous research papers published in the last several decades have emphasized the significance of TFET, yet, achieving low ON-current and fabricating metallurgical connections has proven to be challenging. Junctionless TFETs have entered the scene to fulfill the demands of contemporary technologies. The benefits of both junctionless FETs and TFETs are combined in junctionless TFETs. In contrast to MOSFETs, junctionless FET exhibits high ON current and less fluctuation since it lacks a metallurgical junction. Low ON-current is a problem for TFETs, despite their higher SS. JLTFETs operate under the premise that charge plasma can induce source and drain areas.

Objective of the Invention:
The primary objective of the present invention is to overcome the drawback associated with prior art.
An objective of the present invention is to provide an Analog/RF Performance Analysis of a Novel Si0.9Ge0.1/InAs Charge Plasma Based Junctionless TFET.
Detailed description of drawings:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:

Fig. 1: Illustrate DEVICE STRUCTURE AND DIMENSIONS
Detailed description:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.

It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.

The terms "comprises", "comprising", "includes", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The present invention provides a charge plasma-based hetero structure?junctionless TFET using novel?coalescence?of Si1-xGex/InAs with HfO2 and SiO2 assembled at the gate terminal. Si1-xGex is employed in the source part, while InAs is incorporated in the channel and drain portions. In this paper, simulations are accomplished through the Silvaco-ATLAS software?to explore different device parameters. At standard temperature (300K), the characteristics of the suggested device, DMG-HJLTFET, are analyzed, and its analog/RF?performance is compared to that of traditional Si-JLTFET. The proposed device performs better than the existing ones according to all the criteria and traits.
The remaining segment of the invention is arranged in this way:?device description is discussed?in segment II, segment III examines simulation results, and?? Segment IV discusses important outcomes of the paper.
II. DEVICE STRUCTURE AND DIMENSIONS
Fig. 1 depicts the graphical outlook of (a) our suggested device, dual material?gate hetero-structure?junctionless TFET (DMG-HJLTFET), and (b) traditional homo-material Si-JLTFET. Both devices have a lateral n-type JLTFET architecture with a uniformly doped semiconductor body with a concentration of 1x10-19. DMG-HJLTFET and Si-JLTFET work on the charge plasma concept in which two gate is used, named polar gate (PG) and control gate (CG). PG is situated above the source and has a higher work function; on the other hand, CG is located above the channel and has a lower work function. The main objective of these gates is to convert an exceedingly doped n+-n+-n+ structure into a p+-i-n+ typical structure. Table I, lists the device's structural parameters. The control gates and the polar gate's respective work functions are 4.5 eV and 5.93 eV.
Both devices have a body thickness of 3 nm and a channel length of 20 nm. As dielectric materials, HfO2 and SiO2, 1 nm thickness of each are used in DMG-HJLTFET, whereas SiO2 of 2 nm breadth is applied as a dielectric material in Si-JLTFET. In order to isolate PG and CG, the gap width is kept at 2 nm. Both devices maintain the same doping concentration of 1x1019cm-3. To achieve the necessary polarity of the source, channel, and drain sections the charged plasma concept is incorporated, and the doping concentration is set to be consistent.
TABLE I. Parameters Incorporated in Simulated Structure

DMG-HJLTFET
Device Parameters Value Units
PG Length (LPG) 18 nm
CG Length (LCG) 20 nm
Body Thickness (TBODY) 3 nm
PG work function 5.93 eV
CG work function 4.5 eV
Gap among PG and CG (LSP) 2 nm
The SILVACO-ATLAS software is used for simulations . Non-local band-to-band tunneling model is incorporated because TFET utilizes the tunneling barrier to work on the band-to-band tunneling process. The electric field at each mesh node of the simulated architecture is unrelated to the non-local models. It depends on the device's band structure as well as the bands' spatial fluctuation. The Auger recombination model and band gap narrowing (BGN) are also used. The trap-assisted tunneling model is also applied to consider the impacts of traps. The SRH recombination model is adopted because of the high impurity concentration in the channel region. Additionally used are the CVT model (Lombardi) and Fermi-Dirac statistics. The parallel, perpendicular, temperature- and concentration-dependent electric field mobility are all included in the CVT model. The quantum confinement model proposed by Hansch is also enabled because the body thickness is 3 nm.
The suggested device is simulated and calibrated using the experimental values of a manufactured JLTFET?with a 20?nm gate length, and it also demonstrates the validity of the simulations and models used. The fabrication flow steps of the proposed device DMG-HJLTFET.

Analog and RF parameters of DMG-HJLTFET and Si-JLTFET are discussed in form of transfer characteristics (IDS-VGS), transconductance (gm), total parasitic capacitance (Cgg), maximum oscillation frequency (fmax), gain bandwidth product (GBP), transconductance frequency product (TFP), and Intrinsic Delay.
The parameters mentioned above are being analyzed by Eqn. 1 to Eqn. 6 as discussed below.
1. Transconductance:
gm=?IDS?VGS gm=??IDS??VGS
(1)
2. Total parasitic capacitance:

Cgg=Cgs+Cgd (2)Cgg=Cgs+Cgd (2)

3. Maximum oscillation frequency:

fmax=fT8p(RoutCgd)----------v (3) fmax=fT8??(RoutCgd) (3)

4. Gain bandwidth product:

GBP=gm20pCgd (4)GBP=gm20??Cgd (4)

5. Transconductance frequency product:

TFP=gmIDSXfT (5)TFP=gmIDSXfT (5)

6. Intrinsic delay:

t=CggXVddIDS (6)??=CggXVddIDS (6)

where IDS, VGS, Cgs, Cgd, fT, and Rout represents drain current, gate voltage, the gate to source capacitance, the gate to drain capacitance, cut-off frequency and output resistance respectively
The transfer characteristics of DMG-HJLTFET?and Si-?JLTFET. The use of hetero- material Si1-xGex/InAs?in the source/channel (SE/CL)?regions to implement bandgap engineering results in a wider tunneling barrier breadth?at the SE/CL?contact when no gate bias is applied. As a result, the barrier can only be tunneled by a small number of minority carriers, resulting in very low IOFF. The overlapping of the bands at the SE/CL?contact occurs when the gate voltage is applied?as a result, tunnel barrier width decreases. The ION now increases as more carriers have enough energy to tunnel through the SE/CL contact. Further use of dual dielectric material at the gate enhances the ION and minimizes the IOFF current, as a result, the ION current of DMG-HJLTFET is ~389 times greater in comparison to Si- JLTFET.
gm is a very crucial parameter concerning RF/wireless communications. It is the factor on which the amplification and efficiency of any system depend. For a more significant current conversion rate, gm should be high. The gm of DMG-HJLTFET is 10900% greater than Si-JLTFET, which shows the superiority of DMG-HJLTFET over Si-JLTFET in RF applications.
Fig. 6 shows the comparison of Cgg value among both devices. For smooth RF application, the Cgg value should be low. From the graph, it is clear that the DMG-HJLTFET Cgg value starts to decrease at higher gate voltage, whereas Cgg value of Si-JLTFET continuously increases for the entire gate voltage range.

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