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AN EFFICIENT HIGH SPEED VLSI ARCHITECTURE IN PARALLEL FOR PERFORMING SCALAR MULTIPLICATION IN BINARY
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AN EFFICIENT HIGH SPEED VLSI ARCHITECTURE IN PARALLEL FOR PERFORMING SCALAR MULTIPLICATION IN BINARY
ORDINARY APPLICATION
Published
Filed on 14 September 2021
Patent Information
| Application ID | 202141041241 |
| Date of Application | 14/09/2021 |
Documents
| Name | Date |
|---|---|
| 202141041241-8(i)-Substitution-Change Of Applicant - Form 6 [02-03-2023(online)].pdf | 02/03/2023 |
| 202141041241-ASSIGNMENT DOCUMENTS [02-03-2023(online)].pdf | 02/03/2023 |
| 202141041241-FORM28 [02-03-2023(online)].pdf | 02/03/2023 |
| 202141041241-PA [02-03-2023(online)].pdf | 02/03/2023 |
| 202141041241-FER.pdf | 07/06/2022 |
| 202141041241-Form18_Examination Request_10-01-2022.pdf | 10/01/2022 |
| 202141041241-Form9_Early Publication_22-12-2021.pdf | 22/12/2021 |
| 202141041241-Abstract_As Filed_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Claims_As Filed_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Description Complete_As Filed_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Drawing_As Filed_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Form 2(Title Page)Complete_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Form-1_As Filed_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Form-3_As Filed_14-09-2021.pdf | 14/09/2021 |
| 202141041241-Form-5_As Filed_14-09-2021.pdf | 14/09/2021 |
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