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AN EFFECTIVE VLSI ARCHITECTURE FOR DATA ENCRYPTION STANDARD AND ITS FPGA IMPLEMENTATION
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Abstract
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AN EFFECTIVE VLSI ARCHITECTURE FOR DATA ENCRYPTION STANDARD AND ITS FPGA IMPLEMENTATION
ORDINARY APPLICATION
Published
Filed on 25 September 2021
Patent Information
| Application ID | 202141043525 |
| Date of Application | 25/09/2021 |
Documents
| Name | Date |
|---|---|
| 202141043525-FER.pdf | 06/06/2022 |
| 202141043525-COMPLETE SPECIFICATION [25-09-2021(online)].pdf | 25/09/2021 |
| 202141043525-DECLARATION OF INVENTORSHIP (FORM 5) [25-09-2021(online)].pdf | 25/09/2021 |
| 202141043525-DRAWINGS [25-09-2021(online)].pdf | 25/09/2021 |
| 202141043525-FORM 1 [25-09-2021(online)].pdf | 25/09/2021 |
| 202141043525-FORM 18 [25-09-2021(online)].pdf | 25/09/2021 |
| 202141043525-FORM-9 [25-09-2021(online)].pdf | 25/09/2021 |
| 202141043525-STATEMENT OF UNDERTAKING (FORM 3) [25-09-2021(online)].pdf | 25/09/2021 |
