AN ACTIVE GATE DRIVING SYSTEM AND METHOD FOR THE VOLTAGE BALANCING OF SERIES CONNECTED GAN DEVICES FOR HIGHER VOLTAGE APPLICATION

Abstract

ABSTRACT The present invention relates to an active gate driving system and method for the voltage balancing of series connected gallium nitride (GaN) devices for higher voltage application. The system allows the devices to increase their voltage blocking capability, and be a valid alternative to the multilevel topologies. Hence reducing the number of components and heatsink required in the circuit for the operation. It is useful for high voltage and power application, simple, lower switching and conduction losses.

Specification

Description:FIELD OF INVENTION:
[001] The present invention relates to the field of voltage balancing of series connected devices. The present invention in particular relates to the voltage balancing system and method for the series connected devices.
DESCRIPTION OF THE RELATED ART:
[002] Gallium Nitride (GaN) devices, while being the most power-dense, face a significant challenge in their commercial use due to their low voltage blocking capabilities. To overcome this, these devices can be connected in series. However, the presence of parasitic capacitances and pulse propagation delays in the driving circuit often leads to improper voltage division between the devices, resulting in a voltage imbalance. This imbalance not only hampers the optimal utilization of the semiconductor device but also reduces its lifetime and, in extreme cases, can lead to complete device failure. This issue is most prominent in GaN devices due to their lower transition times.
[003] Reference may be made to the following:
[004] Publication no. US11552549B2 relates to a voltage balancing circuit for use in a power converter is described. In one example, a power converter includes series-connected switching transistors for power conversion and a voltage-balancing control loop. The voltage balancing control loop includes a measurement circuit electrically coupled to a transistor in the pair of series-connected switching transistors. The measurement circuit is electrically coupled to measure a body voltage reference of the transistor. The voltage balancing control loop also includes a balancing circuit configured to generate a balancing pulse signal for adjusting a voltage across the transistor using the body voltage reference and a circuit configured to combine the balancing pulse signal with a gate drive pulse signal for the transistor, to form a balanced gate drive pulse signal for the transistor. The balanced gate drive pulse signal helps to equalize the body diode voltages of the series-connected switching transistors, particularly during "off" periods.
[005] Publication no. US10230354B2 relates to a method for voltage balancing series-connected power switching devices (IGBTs), each connected in parallel with a respective diverter having controllable impedance to controllably conduct current diverted from the associated power switching device, the method comprising the step of controlling each diverter to follow a series of at least two successively higher impedance states during an OFF period of the power switching devices. The series of impedance states for each diverter comprises a first impedance and then a second, higher impedance, the first impedance occurring in response to an indication of the start of the OFF period. The first impedance state preferably occurs during a tail current of the power switching device in parallel with the respective diverter and the second or later impedance state during a leakage current of that power switching device.
[006] Publication no. US11552550B2 relates to a voltage balance circuit including first and second semiconductor devices connected in series with each other is provided with a first transformer having a primary winding and a secondary winding, a second transformer having a primary winding and a secondary winding. A pair of capacitors connected in series with each other and connected between the output terminals of the plurality of semiconductor devices. A first control signal is applied to the control electrode of the first semiconductor device via the primary winding of the first transformer. A second control signal is applied to the control electrode of the second semiconductor device via the primary winding of the second transformer, with one end of each secondary winding connected to each other.
[007] Thus series-connected devices are an alternative to MLIs (Multilevel Inverter) for increasing the voltage capacities of the devices. However, they experience the steady state unbalance and voltage overshoot during the switch-off and the switch-on period respectively.
[008] The existing voltage balancing technique for the series-connected devices is proposed for the Si IGBTs and SiC devices. The existing techniques also require a computation heavy controller and additional bulky components (for e.g., transformers, inductors, digital controllers etc).
[009] In order to overcome above listed prior art, the present invention aims to provide active gate driving system and method for the voltage balancing of series connected gallium nitride (GaN) devices for higher voltage application.
OBJECTS OF THE INVENTION:
[010] The principal object of the present invention is to provide active gate driving system and method for the voltage balancing of series connected gallium nitride (GaN) devices for higher voltage application.
[011] Another object of the present invention is to provide a system that allows the devices to increase their voltage blocking capability, and be a valid alternative to the multilevel topologies.
[012] Yet another object of the present invention is to propose a system which reduces the number of components and heat sink required in the circuit for the operation.
[013] Still another object of the present invention is to propose a system and method which negates the effect of both parasitic gate capacitances and the gate pulse propagation delays.
SUMMARY OF THE INVENTION:
[014] The present invention relates to an active gate driving system and method for the voltage balancing of series connected gallium nitride (GaN) devices for higher voltage application. The proposed system works on GaN devices, where the issue of voltage imbalance is much more prominent due to faster switching rate. Also, the controlling circuit is comprised of capacitor and BJTs and hence is much more compact and doesn't require any costly and computation heavy controller.
[015] The system allows the devices to increase their voltage blocking capability, and be a valid alternative to the multilevel topologies. Hence reducing the number of components and heatsink required in the circuit for the operation. It is useful for high voltage and power application, simple, lower switching and conduction losses.
[016] The proposed system and method increases the voltage blocking capabilities of the converter and is suitable for low voltage high current applications, such as EV applications, UPS applications etc. while also reducing the need for device footprints, space requirement and heat sink requirement.
[017] The balancing circuit is comprised of a capacitor and a network of four BJTs. As the balancing circuit doesn't involve any resistive element, no additional significant losses are added to the system. As the current injection is completely controlled by the analog circuit, there is no need for any computation heavy controllers. It negates the effect of both parasitic gate capacitances and the gate pulse propagation delays.
[018] The steady state voltage unbalance of the series-connected devices during the off-state period was limited within the accepted limit of ±10%. The voltage overshoot experienced by the slower transitioning switch of the series-connected devices was also simultaneously reduced.
BREIF DESCRIPTION OF THE INVENTION
[019] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered for limiting of its scope, for the invention may admit to other equally effective embodiments.
[020] Figure 1 shows (a) depicts various parasitic capacitances present in the series-connected GaN devices; (b) depicts simplified equivalent parasitic capacitances present in the series-connected GaN devices;
[021] Figure 2 depicts the proposed dynamic voltage balancing schematic for the series-connected GaN devices;
[022] Figure 3 depicts the control circuit of the proposed dynamic voltage balancing circuit for the series-connected GaN devices;
[023] Figure 4 (a) depicts the steady-state unbalance voltage and voltage overshoot of the series-connected GaN devices before using the proposed technique at DC link voltage = 100 V and peak drain current = 10 A; (b) depicts the steady-state balance voltage obtained after using the proposed technique at DC link voltage = 100 V and peak drain current = 10 A;
[024] Figure 5 (a) depicts the steady-state unbalance voltage of the series-connected GaN devices before using the proposed technique at DC link voltage = 50 V and peak drain current = 4 A; (b) depicts the steady-state balance voltage obtained after using the proposed technique at DC link voltage = 50 V and peak drain current = 4 A;
[025] Figure 6 (a) depicts the steady-state unbalance voltage of the series-connected GaN devices before using the proposed technique at DC link voltage = 10 V and peak drain current = 1 A; (b) depicts the steady-state balance voltage obtained after using the proposed technique at DC link voltage = 10 V and peak drain current = 1 A;
[026] Figure 7 depicts the voltage balancing of the series-connected GaN devices in the presence of variable drain current;
[027] Figure 8 depicts the pulse propagation delay of 20ns present in the series-connected GaN devices.
DETAILED DESCRIPTION OF THE INVENTION:
[028] The present invention provides an active balancing system and method using an analog voltage balancing circuit, comprising of a capacitor and BJTs, to detect the voltage unbalance across the series-connected switches and inject a current to the gate of the gallium nitride (GaN) switch to control the switching rate of the devices. This injected current cancels out the effect of parasitic gate capacitances and the pulse propagation delays that might be present between the devices, hence increasing the voltage blocking capabilities and reducing the voltage overshoot experienced by the GaN devices.
[029] A capacitive elements (102_5) are connected to the drain of both the top (100_2) and the bottom (100_1) device. The magnitude of the current flowing through (102_5) will be proportional to the rate of change of the drain-source voltage for their respective devices. This helps to determine the rate of transition of the switching state of the device. After detecting the switching rates of each individual device, an appropriate gate current is injected into each gate driver (104) and (105) switch to control their transition times, hence reducing the voltage unbalance event to the permissible limit of ±10%.
[030] The gate current injection circuit (102) and (103) is connected to each device and is comprised of a network of three npn BJTs and one pnp BJT, forming a current mirror. Depending upon the base voltage of the PNP BJT, the capacitor current is appropriately divided and injected into the gate of the switches.
[031] Figure 1.(a) depicts the various parasitic capacitances present in the circuit of the series connected GaN devices (100_1) and (100_2), namely the parasitic capacitance between the drain of the devices and the DC link; the parasitic capacitance between the gate of the devices and the DC link; the parasitic capacitance between the source of the devices and the DC link; the parasitic capacitance between the gate of the devices and the heatsink; and the parasitic capacitance between the heatsink of the devices and the DC link. As the gate pulse propagation delay only depends on gate parasitic capacitance values, Figure 1.(b) depicts the simplified equivalent gate parasitic capacitances considered in the disclosure.
[032] Figure 2 depicts the schematic representation of the proposed dynamic voltage balancing circuit for the series-connected GaN devices. The top switch (100_2) and the bottom switch (100_1) are connected in a series fashion. (100_21) and (100_11) are the parasitic gate capacitance connected across the switches (100_2) and (100_1), respectively. ic1 and ic2 are the parasitic capacitor currents flowing through the (100_21) and (100_11), respectively. These ic1 and ic2 currents are one of the main reasons for the voltage unbalance across the series-connected devices. id1 and id2 are the driver currents injected to/delivered by the respective gate drivers (104) and (105). ig1 and ig2 are the gate currents of the switches (100_1) and (100_2) respectively.
[033] Figure 3 depicts the control circuit of the proposed dynamic voltage balancing circuit for the series-connected GaN devices (100_1) and (100_2). In the proposed technique, a small external control miller capacitor (102_5) is connected across the drain terminal of both switches. Depending on the magnitude of the control capacitor and the rate of change of voltage across the switch, a miller current will flow through this miller control capacitor. Now, to inject an adequate current online using this control technique, which could compensate for the effect of both the gate parasitic current and the pulse delay across both switches, a network of four identical BJTs (102_1)-(102_4) is used to form a current mirror. Depending on the magnitude of the Vctrl, the current mirror divides the miller current and injects it back into the switch, hence controlling their rate of transition.
[034] Figure 4- Figure 7 shows the hardware validation result of the proposed technique. Figure 4 (a) depicts the steady-state unbalance voltage and voltage overshoot of the series-connected GaN devices before using the proposed technique at DC link voltage = 100 V and peak drain current = 10 A. It can be observed that when the technique was not applied to the series-connected GaN devices, the voltage unbalance of 51.5V was obtained between the switches, and during the turn-on transition, the bottom device experienced the peak overshoot voltage of 70V. Figure 4 (b) depicts the steady-state unbalance voltage and voltage overshoot of the series-connected GaN devices at DC link voltage = 100 V and peak drain current = 10 A. The steady state unbalance was reduced to 3 V (~94% reduction), and the voltage overshot was reduced to 5 V (~92% reduction). A similar study was done for the DC link voltage = 50 V and peak drain current = 4A (Figure 5 (a) and (b)); and for the DC link voltage = 10 V and peak drain current = 1 A (Figure 5 (a) and (b)). The steady state voltage unbalance was reduced from 8.5 V to 1.75 V (~80% reduction), as depicted in Figure 5, and from 3.5 V to 0.5 V (~86% reduction), as depicted in Figure 6.
[035] Figure 7 depicts the voltage balancing of the series-connected GaN devices (100_1) and (100_2) in the presence of variable drain current. Here, five pulses of 25% duty ratio were passed through the series-connected GaN switches (100_1) and (100_2), and the voltage balance was obtained under the variable load current case.
[036] All the obtained results are well within the acceptable limit of ±10% of the applied DC link. The experiments were done in the presence of parasitic capacitances (100_11), (100_12), (100_21) and (100_21), and the pulse propagation delay of 20 ns was present in the series-connected GaN devices (100_1) and (100_2), as depicted in Figure 9.
[037] The proposed technique is robust enough to obtain voltage balancing of the series connected switches even in the presence of moderate loop inductances, gate parasitic capacitances, and gate pulse propagation delays. It enables the GaN devices to increase their original voltage-blocking capabilities. The proposed method, being non-resistive, does not increase any significant losses in the system. It doesn't require any complex, computation-heavy controller.
[038] Numerous modifications and adaptations of the system of the present invention will be apparent to those skilled in the art, and thus it is intended by the appended claims to cover all such modifications and adaptations which fall within the true spirit and scope of this invention.
, Claims:WE CLAIM:
1. An active gate driving system and method for the voltage balancing of series connected GaN devices for higher voltage application comprises-
a) Series connected GaN devices (100_1) and (100_2), characterized in that the parasitic capacitance between the drain of the devices and the DC link; the parasitic capacitance between the gate of the devices and the DC link; the parasitic capacitance between the source of the devices and the DC link; the parasitic capacitance between the gate of the devices and the heatsink; and the parasitic capacitance between the heatsink of the devices and the DC link.
b) The top switch (100_2) and the bottom switch (100_1) connected in a series fashion.
c) Parasitic gate capacitance (100_21) and (100_11) connected across the switches (100_2) and (100_1), respectively.
d) Parasitic capacitor ic1 and ic2 wherein the currents flowing through the (100_21) and (100_11), respectively.
e) Driver currents id1 and id2 injected to/delivered by the respective gate drivers (104) and (105).
f) Gate currents ig1 and ig2 of the switches (100_1) and (100_2) respectively.
g) A small external control miller capacitor (102_5) is connected across the drain terminal of both switches.
h) A network of four identical BJTs (102_1)-(102_4) characterized in that an analog current injection voltage balancing circuit made of three NPN and one PNP configuration, forming a current mirror.
2. The active gate driving system and method for the voltage balancing of series connected GaN devices, as claimed in claim 1, wherein the miller current flows through the miller control capacitor depending on the magnitude of the control capacitor and the rate of change of voltage across the switch.
3. The active gate driving system and method for the voltage balancing of series connected GaN devices, as claimed in claim 2, wherein to inject an adequate current online using this control technique, which could compensate for the effect of both the gate parasitic current and the pulse delay across both switches, a network of four identical BJTs (102_1)-(102_4) is used to form a current mirror and depending on the magnitude of the Vctrl, the current mirror divides the miller current and injects it back into the switch and controls their rate of transition.
4. The voltage balancing of the series-connected GaN devices in the presence of variable drain current, as claimed in claim 1, wherein five pulses of 25% duty ratio were passed through the series-connected GaN switches (100_1) and (100_2), and the voltage balance was obtained under the variable load current case.
5. The voltage balancing of the series-connected GaN devices in the presence of variable drain current, as claimed in claim 1, wherein during the turn-on and turn-off transition of the device, a current flows through the miller capacitor (102_5) and current mirror circuit (102_1)-(102_4) diverts a part of the miller current back to the gate of the device (104) and (105) and portion of the miller current to be fed back to the gate of the device can be controlled by the control voltage of the current mirror.
6. The voltage balancing of the series-connected GaN devices in the presence of variable drain current, as claimed in claim 1, wherein during the turn-on transition, an opposite current is flown to the gate driver by the analog current injection voltage balancing circuit (102_1)-(102_4) to slow down the turn-on instance of the fast switching device and slow switching device is forced to transition faster by injecting a positive current to the gate driver.

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