A Switched Capacitor 25-Level Inverter (SC25LI) System For Solar Power Applications

Abstract

The present invention is related to a switched capacitor 25-level inverter (SC25LI) system for solar power applications. The Switched Capacitor 25-Level Inverter (SC25LI) system (100) is an advanced inverter design aimed at efficient voltage gain and high power quality with minimal components. It comprises a modified H-bridge (110) with four complementary switch pairs; two asymmetrical DC voltage sources (120) with a 1:2 ratio, two capacitors (130), and two diodes (140). With twelve switches (150) arranged in six complementary pairs, the SC25LI achieves a voltage gain of 2 and self-balancing capability, eliminating the need for auxiliary balancing circuits. The system utilizes Sinusoidal Pulse Width Modulation (SPWM) to control output voltage levels, producing 25 discrete voltage levels from 0Vdc to ±12Vdc/5. Designed for renewable energy applications, including grid-connected solar PV sources, the SC25LI efficiently supports dynamic load conditions.

Specification

Description:Figure 1 illustrates the topology of a switched capacitor 25-level inverter (SC25LI) system. The Switched Capacitor 25-Level Inverter (SC25LI) topology is an innovative inverter design that achieves a high voltage gain using fewer system components. Specifically, the SC25LI provides a voltage gain of 2, doubling the input voltage without needing additional boost circuits. This high gain, combined with a streamlined component layout, enables efficient power conversion in a compact setup.
The SC25LI system includes a minimal configuration of 12 switches, two capacitors, two diodes, and two DC sources, which collectively enable the generation of 25 distinct voltage levels. By reducing the component count, the topology simplifies the design and reduces overall costs while still achieving high-quality, stable power output. One of the unique features of this topology is its self-balancing capability for capacitors, meaning it does not require any external circuit for maintaining voltage balance, thereby enhancing the system's reliability and ease of operation.
To efficiently manage the switching operation, the SC25LI topology organizes its 12 switches into six complementary pairs: (S1, S4), (S2, S3), (S5, S6), (S7, S10), (S9, S8), and (S11, S12). Each pair operates in a complementary manner, where one switch in the pair is on while the other is off. This pairing helps control the current and voltage levels, making it possible to achieve a 25-level output waveform. The system requires only six gate pulses to control these pairs, further simplifying the control architecture.
The 25-level output of the SC25LI is generated using two asymmetrical DC voltage sources, two diodes, two capacitors, and the six pairs of complementary switches. This configuration enables the production of a stepped waveform that approximates a sinusoidal form, reducing harmonic distortion and providing high-quality power output.
Table 1: Switching logic and states for the proposed SC25LI topology

NOTE: VDC1 = Vdc, VDC2 = Vdc/5, 1 - ON switch, 0 - OFF switch, FB - Forward bias, RB - Reverse bias, C - Charging, D - Discharging, NC - No Change
Operating Modes of proposed SC25LI topology:
Mode 1: The Zero output voltage is generated, if the switches S2, S4, S5, S8, S10 and S11 are in conduction state, while the rest switches are in non-conduction state. Capacitor C1 is charged to Vdc/5 through S5 and the capacitor C2 is charged to Vdc through switch S11. The conduction diagram of Zero load Voltage is shown in Fig 2.2(a).
The output voltage, V load =0.
Mode 2: The switches S3, S4, S5, S8, S10 and S11 are in conduction mode and remaining are non conducting. In this mode the capacitors C1 and C2 are in ideal state. The conduction diagram is shown in Fig 2.2(b).
The output voltage, V load = VDC2 = Vdc/5.
Mode 3: During this mode the switches S3, S4, S6, S8, S10 and S11 are in conduction state, whereas other switches are in non-conducting state shown in Fig 2(c). In this case the capacitor C1 is discharged through S6 and which is in series with the VDC2 voltage source, The capacitor C2 is experience no charge.
The output voltage, V load = VDC2 + VC1 = 2Vdc/5.
Mode 4: The switches S1, S2, S5, S9, S10 and S11 are in conduction state and remaining switches are in non-conduction path. The capacitor C1 discharges through S6 and C2 capacitoris ideal. The conduction path of this mode is shown in Fig 2(d).
The output voltage, V load = VDC1 - VDC2 -VC1 = 3Vdc/5.
Mode 5: In this mode, switches S1, S2, S5, S9, S10 and S11 are in conducting state, whereas the other switches are in non-conducting state is shown in Fig 2(e). The capacitor C1 is equal with the VDC2 voltage source and capacitor C2 is ideal.
The output voltage, V load = VDC1 - VDC2 = 4Vdc/5.
Mode 6: During this mode, switches S2, S4, S5, S9, S10 and S11 are in the conduction state and remaining switches are non-conduction state. The capacitor C1 and C2 experience no charge during this mode. The conduction path is shown Fig 2(f).
The output voltage, V load = VDC1 = Vdc.
Mode 7: The switches S3, S4, S5, S9, S10 and S11 are in conduction state and remaining switches are in non-conduction path. The capacitor C1 and C2 capacitoris ideal. The conduction path of this mode is shown in Fig 2(g).
The output voltage, V load = VDC1 + VDC2 = 6Vdc/5.
Mode 8: During this mode the switches S3, S4, S6, S9, S10 and S11 are in conduction state, whereas other switches are in non-conducting state shown in Fig 2(h). In this case the capacitor C1 is discharged through S6 and which is in series with the VDC2 voltage source, The capacitor C2 is experience no charge.
The output voltage, V load = VDC1 + VDC2 + VC1 = 7Vdc/5.
Mode 9: In this mode, switches S1, S2, S6, S9, S10 and S12 are in conducting state, whereas the other switches are in non-conducting state is shown in Fig 2(i). The capacitor C1 and VDC2 voltage source are in series connection and it discharges through S6. Similarly, capacitor C2 comes in series with the VDC1 voltage source and discharges through switch S12.
The output voltage, V load = VDC1 + VC2 - VDC2 -VC1 = 8Vdc/5.
Mode 10: The switches S1, S2, S5, S9, S10 and S12 are in conducting state, the remaining switches are in non-conducting state is shown in Fig 2(j). The capacitor C1 is charged to VDC2 voltage source through S5 and capacitor C2 remains in series with VDC1 and discharges through switch S12.
The output voltage, V load = VDC1 + VC2 - VDC2 = 9Vdc/5.
Mode 11: During this mode the switches S2, S4, S5, S9, S10 and S12 are in conduction state, whereas other switches are in non-conducting state shown in Fig 2(k). In this case the capacitor C1 is ideal, capacitor C2 comes in series with the VDC1 and discharges through S12.
The output voltage, V load = VDC1 + VC2 = 2Vdc.
Mode 12: In this mode, switches S3, S4, S5, S9, S10 and S12 are in conducting state is shown in Fig 2(l), while the other switches are in non-conducting state. The capacitor C1 experience no charge, capacitor C2 comes in series with the VDC1 voltage source and discharges through switch S12.
The output voltage, V load = VDC1 + VC2 + VDC2= 11Vdc/5.
Mode 13: The switches S3, S4, S6, S9, S10 and S12 are in conducting state, the remaining switches are in non-conducting state is shown in Fig 2(m). The capacitor C1, VDC2 voltage source are in series and discharges through S6, similarly capacitor C2 comes in series with VDC1 and discharges through switch S12.
The output voltage, V load = VDC1 + VC2 + VDC1 + VC1= 12Vdc/5.
Mode 14: During this mode, switches S1, S2, S5, S7, S9 and S11 are in conduction state, while the other switches are in non-conduction state shown in Fig 2(n). The Capacitor C1 is charged to Vdc/5 through S5 and the capacitor C2 is charged to Vdc through switch S11.
The output voltage, V load = - VDC2 = -Vdc/5.
Mode 15: In this mode, switches S1, S2, S6, S7, S9 and S11 are in conduction state, whereas other switches are in non-conducting state shown in Fig 2(o). In this case the capacitor C1 is discharged through S6 and which is in series with the VDC2 voltage source, The capacitor C2 is experience no charge.
The output voltage, V load = - VDC2 - VC1 = - 2Vdc/5.
Mode 16: The switches S3, S4, S6, S7, S8 and S11 are in conduction state and remaining switches are in non-conduction path. The capacitor C1 discharges through S6 and C2 capacitoris ideal. The conduction path of this mode is shown in Fig 2(p).
The output voltage, V load = - VDC1 + VDC2 + VC1 = - 3Vdc/5.
Mode 17: In this mode, switches S3, S4, S5, S7, S8 and S11 are in conducting state, whereas the other switches are in non-conducting state is shown in Fig 2(q). The capacitor C1 is equal with the VDC2 voltage source and capacitor C2 is ideal.
The output voltage, V load = - VDC1 + VDC2 = - 4Vdc/5.
Mode 18: During this mode, switches S1, S3, S5, S7, S8 and S11 are in the conduction state and remaining switches are non-conduction state. The capacitor C1 and C2 experience no charge during this mode. The conduction path is shown Fig 2(r).
The output voltage, V load = - VDC1 = - Vdc.
Mode 19: The switches S1, S2, S5, S7, S8 and S11 are in conduction state and remaining switches are in non-conduction path. The capacitor C1 and C2 capacitor is ideal. The conduction path of this mode is shown in Fig 2(s).
The output voltage, V load = - VDC1 - VDC2 = - 6Vdc/5.
Mode 20: During this mode the switches S1, S2, S6, S7, S8 and S11 are in conduction state, whereas other switches are in non-conducting state shown in Fig 2(t). In this case the capacitor C1 is discharged through S6 and which is in series with the VDC2 voltage source, The capacitor C2 is experience no charge.
The output voltage, V load = - VDC1 - VDC2 - VC1 = - 7Vdc/5.
Mode 21: In this mode, switches S3, S4, S6, S7, S8 and S12 are in conducting state, whereas the other switches are in non-conducting state is shown in Fig 2(u). The capacitor C1 and VDC2 voltage source are in series connection and it discharges through S6. Similarly, capacitor C2 comes in series with the VDC1 voltage source and discharges through switch S12.
The output voltage, V load = - VDC1 - VC2 + VDC2 + VC1 = - 8Vdc/5.
Mode 22: The switches S3, S4, S5, S7, S8 and S12 are in conducting state, the remaining switches are in non-conducting state is shown in Fig 2(v). The capacitor C1 is charged to VDC2 voltage source through S5 and capacitor C2 remains in series with VDC1 and discharges through switch S12.
The output voltage, V load = - VDC1 - VC2 + VDC2 = - 9Vdc/5.
Mode 23: During this mode the switches S1, S3, S5, S7, S8 and S12 are in conduction state, whereas other switches are in non-conducting state shown in Fig 2(w). In this case the capacitor C1 is ideal, capacitor C2 comes in series with the VDC1 and discharges through S12.
The output voltage, V load = - VDC1 - VC2 = - 2Vdc.
Mode 24: In this mode, switches S1, S2, S5, S7, S8 and S12 are in conducting state is shown in Fig 2(x), while the other switches are in non-conducting state. The capacitor C1 experience no charge, capacitor C2 comes in series with the VDC1 voltage source and discharges through switch S12.
The output voltage, V load = - VDC1 - VC2 - VDC2 = - 11Vdc/5.
Mode 25: The switches S1, S2, S6, S7, S8 and S12 are in conducting state, the remaining switches are in non-conducting state is shown in Fig 2(y). The capacitor C1, VDC2voltage source are in series and discharges through S6, similarly capacitor C2 comes in series with VDC1 and discharges through switch S12.
The output voltage, V load = - VDC1 - VC2 - VDC1 - VC1= - 12Vdc/5.
, Claims:We claim
1. A switched capacitor 25-level inverter (SC25LI) system (100) comprising:
a) a modified H-bridge (110) with four complementary switch pairs;
b) two asymmetrical direct current (DC) voltage sources (120), two capacitors (130), and two diodes (140);
c) a configuration of twelve switches (150) arranged in six complementary pairs; and
d) wherein the SC25LI topology provides a voltage gain of 2 and wherein the configuration does not require an auxiliary circuit for balancing capacitor voltage, enabling self-balancing capability.
2. The SC25LI system as claimed in claim 1, wherein the twelve switches form six complementary pairs, namely (S1, S4), (S2, S3), (S5, S6), (S7, S10), (S9, S8), and (S11, S12), such that each pair operates in a complementary manner to generate 25 discrete voltage levels for output.
3. The SC25LI system as claimed in claim 1, further comprises two capacitors that operate as switched capacitors, wherein said capacitors maintain inherent voltage balance during inverter operation, thereby eliminating the need for external voltage sensors or balancing circuits.
4. The SC25LI system as claimed in claim 1, wherein the system utilizes a Sinusoidal Pulse Width Modulation (SPWM) technique for controlling the output voltage levels, achieving high-resolution voltage levels from 0Vdc to ±12Vdc/5 in increments of Vdc/5.

5. The SC25LI system as claimed in claim 1, wherein the inverter topology is configured for renewable energy applications, including grid-connected distributed energy sources, allowing integration with systems generating power from solar photovoltaic (PV) sources and maintaining dynamic modulation capabilities for variable load conditions.

6. The SC25LI system as claimed in claim 1, wherein the left unit circuit comprises switches S5 and S6 to produce voltage levels of Vdc/5 and 2Vdc/5, and the right unit circuit comprises switches S11 and S12 to produce voltage levels of Vdc and 2Vdc, forming a stepped output with fewer switches and optimized voltage distribution.

7. The SC25LI system as claimed in claim 1, wherein the asymmetrical DC voltage sources are configured with a magnitude ratio of 1:2, providing a balanced output while minimizing the total number of components required to achieve a 25-level stepped output waveform.

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