A Single-Source Thirteen-Level Inverter (SSTLI) System for Solar PV Applications

Abstract

The present invention is related to a single-source thirteen-level inverter (SSTLI) system for solar PV applications. The SSTLI is an advanced multilevel inverter topology designed to generate high-quality AC output from a single DC source. Using a modular unit (MU) with an H-bridge structure and integrated self-balancing capability, the SSTLI achieves a boost factor of 1.5 and delivers thirteen distinct voltage levels without requiring external balancing circuits. Key features include complementary switch pairs (S4, S11), (S3, S10), and (S2, S), which simplify control and reduce voltage stress across components. Capacitors C3 and C4 maintain voltages at Vdc, while C1 and C2 hold 0.5 Vdc, supporting stable output and improved efficiency. This modular approach minimizes component count, resulting in a compact, reliable inverter that performs effectively under different load types, such as R-load and RL-load. The SSTLI offers significant advantages in renewable energy and other applications where high-quality, multilevel AC power conversion is essential.

Specification

Description:Figure 1 illustrates the topology of a single-source thirteen-level inverter (SSTLI) system for solar PV applications. The single-source thirteen-level inverter (SSTLI) system is designed for solar PV applications, featuring an innovative approach to generating a high-quality AC output from a single DC input source (100). The system comprises a modular unit (MU) with a transistor-clamped H-bridge configuration, which enables the generation of thirteen distinct voltage levels through a systematic switching of multiple levels. This configuration includes a set of capacitors-specifically, C3 and C4, which are coupled to the input source and maintain a steady voltage of Vdc, along with capacitors C1 and C2 that hold 0.5 Vdc-ensuring stable voltage distribution across the inverter. Additionally, complementary switch pairs provide inherent self-balancing capability, eliminating the need for external voltage-balancing circuits.
The SSTLI's modular unit incorporates a bi-directional switch (S5), designed as either a transistor-diode series pair or a back-to-back transistor setup, to enable controlled clamping With in the H-bridge structure. This unit also includes complementary switch pairs, such as (S4, S11), (S3, S10), and (S2, S), which simplify control and reduce switching complexity, allowing seamless operation across the thirteen levels. Achieving a voltage gain of 1.5, the SSTLI reaches a peak output voltage of 3 Vdc, providing a robust and consistent AC output suitable for differential phase voltages and load currents across both resistive and resistive-inductive (RL) loads.
The modular structure enables the SSTLI to generate a balanced 13-level stepped output waveform, featuring both positive and negative half-cycles through sequential switching. This configuration allows for smooth transitions between output levels and reduced voltage stress on each switch, thereby enhancing system durability. Further, the system's efficiency is amplified by its reduced component count, which minimizes total standing voltage (TSV) and switching losses while maintaining efficient voltage regulation across all output levels. This efficient, compact SSTLI system is well-suited for high-quality power delivery in solar PV and other renewable energy applications, as it meets varying power requirements through modulated output tailored to specific application needs.
The 13-level Single-Source Thirteen-Level Inverter (SSTLI) structure is illustrated in Fig. 1, detailing a modular configuration that relies on a single modular unit (MU). This unit includes an H-bridge arrangement, where a transistor in series with a diode, or two transistors linked back-to-back, can serve as a clamping transistor in MU at switch S5. Notably, switch S5 is designed as a bi-directional switch, which allows it to handle current flow in both directions, thus improving flexibility in operation. Within this setup, the MU operates effectively as a transistor-clamped H-bridge, enabling it to produce a layered output by sequentially switching through multiple levels.
The system utilizes a set of capacitors-C3 and C4-which are connected to the single DC input source rated at 2 Vdc. This configuration supports stable operation and enhances voltage regulation. Capacitors C4 and C3 are each charged to maintain a voltage of Vdc, while capacitors C1 and C2 hold a steady 0.5 Vdc, which collectively ensures a balanced voltage distribution across the inverter. The output voltage Vab is produced as a multi-level output waveform, achieving a total of 13 distinct voltage levels, which provides a fine resolution for AC signal generation from the DC source. This design offers a voltage gain of 1.5, meaning the inverter is capable of producing an output voltage 1.5 times the DC input.
Table I summarizes the operational switching states of each transistor in the SSTLI, showing the sequence required to produce each of the 13 voltage levels. This table allows users to understand the precise activation patterns that achieve the desired voltage levels in both the positive and negative half-cycles. This modular, self-balancing design not only reduces component stress by controlling voltage across each switch but also improves efficiency, making it suitable for applications requiring a stable and high-quality AC output from a single DC input.
Table -I Switching logic of 13 level inverter
3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3
S1 1 0 1 0 1 0 0 0 0 0 0 0 0
S2 0 0 1 1 0 0 0 1 1 0 0 1 1
S3 1 1 1 1 0 0 0 1 1 0 0 0 0
S4 0 0 0 0 0 0 0 1 1 1 1 1 1
S5 0 1 0 1 0 1 0 1 0 1 0 1 0
S6 0 0 0 0 0 0 1 0 1 0 1 0 1
S7 0 0 0 0 1 1 1 0 0 1 1 0 0
S8 0 0 1 1 0 0 0 1 1 0 0 0 0
S9 1 1 0 0 1 1 1 0 0 1 1 0 0
S10 0 0 0 0 1 1 1 0 0 1 1 1 1
S11 1 1 1 1 1 1 1 0 0 0 0 0 0

Figures 2 and 3 illustrate the SSTLI's operating modes for various output levels within each half-cycle. During the positive half-cycle (Fig. 2), the SSTLI steps through positive voltage levels, while during the negative half-cycle (Fig. 3), it produces equivalent negative levels. This structure achieves a boost factor of 1.5, allowing a peak output voltage of 3 Vdc when needed. To reduce control complexity, complementary switch pairs, such as (S4, S11), (S3, S10), and (S2, S), are employed. These pairs operate in tandem to simplify switching actions, reducing the number of control signals required and minimizing overall switching complexity.
An analysis of the 13-level SSTLI with MU that exhibit self-balance and 1.5 voltage gains has been provided above. With a single DC supply, the output level may be raised and the boost factor may increase. Under the condition of n MU, the following equation can be used to represent the number of output levels NLevel and the boost factor m:
Nlevel =2n+3 - 3, m = 2 -(1/2n)
The total voltage of Cia and will not be exceeded by the voltage stress on the transistors in MU. A rise of about twice that may be obtained by extending MU.
Inverter modulation techniques play a critical role in controlling multilevel inverters, particularly for three-phase two-level Voltage Source Inverters (VSIs). Basic control methods include the 120° and 180° mode control techniques, which apply constant gate pulses of 120° or 180° duration to each switching device in the three-phase or six-pulse VSI. While these techniques are simple and effective for managing inverter output frequency, they do not allow for control over the output voltage magnitude, which limits their application. For scenarios requiring adjustable output voltage, more sophisticated modulation techniques, such as Pulse Width Modulation (PWM) methods, are employed. Techniques like sinusoidal PWM, space vector PWM, and selective harmonic elimination PWM are well-established in two-level VSIs and have been adapted for multilevel inverters. However, as multilevel inverters involve more switching devices, they bring added complexity to control. Despite this complexity, multilevel topologies also provide additional switching states, which can be advantageous for achieving specific modulation goals. Consequently, a variety of specialized modulation techniques have been developed to cater to different applications and converter topologies, each with unique benefits and trade-offs.
Carrier-based PWM techniques control switching by comparing a reference signal with a high-frequency triangular waveform, also known as the carrier. Carriers can be triangular, saw-tooth, or trapezoidal, with triangular carriers being the most widely used. The reference signal can either be unipolar or bipolar, depending on the desired output waveform. Switching instances are determined when the modulating signal intersects the carrier waveform. Sinusoidal PWM is a common technique in two-level inverters due to its simplicity and low distortion. This approach has been successfully adapted for multilevel inverters, with additional carrier techniques developed to minimize distortion. In multilevel configurations, sinusoidal PWM is extended to incorporate multiple carrier waves, creating two main arrangements: Level-Shifted PWM (LS-PWM) and Phase-Shifted PWM (PS-PWM), which enable smoother transitions between multiple voltage levels.
The multilevel carrier based PWM for L-level inverter uses set of L-1 adjacent level triangular carrier waves with same peak-to-peak amplitude and same frequency. The carriers span the whole amplitude range that can be generated by the converter. Three carrier dispositions SPWM strategies are commonly referred as
• Phase Disposition (PD): The carriers are in phase, but level shifted (Fig. 2.18(a)).
• Phase Opposition Disposition (POD): The carriers above zero are in opposition of phase with the carriers below zero (Fig. 2.18(b)).
• Alternative Phase Opposition Disposition (APOD): The carriers are 180 phases shifted from the adjacent carrier (Fig. 2.18(c)).
Phase-shifted PWM (PSPWM) is a natural extension of traditional PWM techniques, specially conceived for FC and CHB converters. The Carrier phase shifted method (PS-PWM) has (L-1) carrier signals with the same amplitude and frequency. A phase shift is introduced between the carrier signals of contiguous cells, producing a phase-shifted switching pattern between them. In this way, when connected together, a stepped multilevel waveform is originated. It has been demonstrated that the lowest distortion can be achieved when the phase shifts between carriers are 180 or 360°/k for a CHB Inverter. (where k is the number of power cells) and 3600/(L-1) for the FCMI introduced across the cells to generate the PWM multilevel output waveform. This difference is related to the fact that the FC and CHB cells generate two and three levels, respectively.
Carrier-based pulse width modulation (PWM) is a common technique used in power electronics to control the switching of power converters such as inverters. The technique involves modulating a high-frequency carrier waveform with a low-frequency reference signal to generate the output waveform. In carrier-based PWM, the carrier waveform is typically a triangular waveform with a fixed frequency, while the reference signal is a sinusoidal waveform representing the desired output voltage. Shift the reference sine wave by the required levels to match the output voltage levels of the inverter. Compare the shifted reference waveform with a triangular carrier waveform of a fixed frequency. The PWM signal consists of a series of pulses with varying widths, depending on the amplitude of the reference signal. The pulses are generated by comparing the reference signal with the carrier waveform and turning on the switch when the carrier waveform is higher than the reference signal, and turning it off when the carrier waveform is lower than the reference signal. The duty cycle of the PWM signal is proportional to the amplitude of the reference signal. By adjusting the duty cycle of the PWM signal, the output voltage of the inverter can be controlled to match the desired waveform. Carrier-based PWM is widely used in power electronics due to its simplicity and effectiveness. In Fig 3 shows the carrier-based pulse width modulation is used for generating the output voltage of five levels. The Modulation technique consists of four triangular waveforms and one sinusoidal reference signal to generate five level inverters.
Similarly, for generating the seventeen-level inverter the modulation technique consists Sixteen triangular carrier pulses with the amplitude of 1V each with a high frequency of 3500Hz and a low frequency sinusoidal reference signal with an amplitude of 8V and 50Hz is used in the proposed topology of Switched Capacitor 17-Level inverter. The Fig 3.1 shows the Modulating signal with Sixteen carrier pulses for seventeen-level inverter. The reference signal is compared with the carrier waveforms. The total of eight carriers are above the zero axis and the remaining are below the zero axis. The phase shift among the carriers is zero in phase disposition technique.
This present invention verifies the proposed SSTLI topology through MATLAB simulation analysis, employing sinusoidal PWM to generate switching pulses for the inverter. The simulation setup includes an RL load with resistance (R) of 100Ω and inductance (L) of 110mH, a DC supply voltage of 200V, and a sampling time of 1/2500 seconds. As the modulation index (M) decreases, the number of voltage levels in the phase output voltage also reduces. Table 2 provides a detailed breakdown of the phase output voltage levels for the 13-level inverter based on varying modulation index values.
Table 2 also compares the Total Harmonic Distortion (THD), RMS voltage (V_RMS), and peak voltage (V_PEAK) for the proposed SSTLI as the modulation index changes. The analysis reveals that the THD of the SSTLI increases as the modulation index decreases, a result of the reduction in step levels in the output phase voltage with lower values of M. Observing the table, we can track the changes in V_PEAK and V_RMS amplitudes as M varies, illustrating how the modulation index impacts voltage output characteristics.
Table 2. Phase voltage levels for SSTLI inverter.
MODULATIONINDEX [M] NO OF
LEVELS VPEAK [V] VRMS [V] THD%
1 13 299 211.4 7.58
0.9 13 269 190.2 9.02
0.8 11 239.1 169.1 10.3
0.7 11 209.2 147.9 10.7
0.6 9 179.4 126.8 14.13
0.5 7 149.6 105.7 14.95
0.4 7 119.4 84.45 20.3
0.3 5 89.71 63.43 28.15
0.2 5 59.72 42.23 34.85
0.1 3 29.72 21.02 92.28











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, Claims:We claim
1. A single-source thirteen-level inverter (SSTLI) system for solar PV applications, the system (100) comprising:
a) a single DC input source configured to provide a base voltage (Vdc);
b) a modular unit (MU) with a transistor-clamped H-bridge arrangement, wherein the MU is configured to produce a thirteen-level output voltage by switching through multiple levels;
c) a set of capacitors, including capacitors C3 and C4 coupled to the input source, each maintaining a voltage level of Vdc, and capacitors C1 and C2 maintaining a voltage level of 0.5 Vdc for stable voltage distribution; and
d) a series of complementary switch pairs configured to achieve self-balancing of voltages across capacitors during operation without requiring external balancing circuits.
2. The inverter system as claimed in claim 1, wherein the MU comprises a bi-directional switch (S5) configured as a transistor in series with a diode or a back-to-back transistor configuration, thereby enabling controlled clamping functionality within the H-bridge structure; and a complementary switching configuration that includes switch pairs (S4, S11), (S3, S10), and (S2, S) to simplify control and reduce switching complexity during inverter operation.
3. The inverter system as claimed in claim 1, wherein the SSTLI system achieves a voltage gain of 1.5, such that the peak output voltage reaches 3 Vdc.
4. The inverter system as claimed in claim 1, wherein the modular unit is capable of generating a 13-level stepped output waveform that includes both positive and negative half-cycles through sequential activation of the complementary switches.
5. The inverter system as claimed in claim 1, wherein the modular unit is configured to supply differential phase voltages and load currents to both resistive (R-load) and resistive-inductive (RL-load) conditions; and the output waveform is modulated based on a specified modulation index to suit application requirements for consistent power delivery.
6. The inverter system as claimed in claim 1, further comprising a set of switching states for each transistor that details the operational modes of the system for each voltage level generated by the SSTLI, wherein the switching states enable smooth transitions between output voltage levels, resulting in reduced voltage stress across each switch component.
7. The inverter system as claimed in claim 1, wherein the system requires fewer components compared to traditional multilevel inverters, thereby reducing total standing voltage (TSV) and minimizing switching loss, while maintaining efficient voltage regulation across all output levels.

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