A POWER FACTOR CORRECTION LED DRIVER CIRCUIT TO PROVIDE CONSTANT OUTPUT CURRENT WITH REDUCED TOTAL HARMONIC DISTORTION

Abstract

A reduced power processing LED driver has been proposed in the present invention as shown in figure-1. Two buck-boost converters are used wherein one buck-boost converter is used as power factor correction (PFC) converter and the other buck-boost converter is used as power control (PC) converter. A rectifier is used which supplies input supply to both converters. The proposed invention achieves a high-power factor (PF) with reduced harmonics on the AC side and flicker-free operation on the DC side. The proposed reduced-power-processing LED driver employs a simple ripple cancellation control technique to eliminate 100 Hz ripple in the LED load current, which aids to increase the lifespan of the LED driver by replacing short-life electrolytic capacitors with long-life film capacitors. Hence, one output capacitor is replaced with two capacitors (split capacitor), fewer semiconductor devices which offers reduced power processing. As a result, the proposed converter design and control technique helps to improve efficiency, decrease cost and size and increase power density.

Specification

Description:DESCRIPTION
FIELD OF THE INVENTION
[0001] The present invention is related to a power factor led driver circuit more particularly using a two-output power factor correction (PFC) converter and a power control (PC) converter.

BACKGROUND:
[0002] Light-emitting diode (LEDs) have a promising prospect due to its outstanding advantages such as long lifetime, high illumination efficiency environmentally friendly, flexibility of color mixing, etc. A constant current driver is needed to support the LED working performance based on the electrical characteristics of LEDs.

[0003] The existing invention discloses a AC/DC PFC converter includes an LLC PFC pre-regulator and a DC/DC converter output stage. The output stage has a feedback unit adapted to provide a feedback signal (in addition to the conventional feedback of the bus voltage error) to the control circuit of the PFC pre-regulator in dependence on the output power and/or the input current and voltage to modulate the controlled output voltage of the PFC pre-regulator. In this way, by controlling the gate switching in the PFC pre-regulator, the total harmonic distortion of the input to the converter can be reduced.

[0004] The prior art provides a regulation for an output voltage of a DC-DC converter. The control variable provided to the controller of the DC converter is composed of a controlled variable of a voltage regulator and a further controlled variable of a pilot control. The controlled variable of the voltage regulator results directly from the comparison of the output voltage with a nominal voltage. Among other things, the controlled variable of the pre control takes into account the input voltage of the DC-DC converter, wherein the value of the DC input voltage can be corrected in such a way that the voltage regulator can be operated in steady-state operation near the zero point. In this way results in a faster and more precise control of the output voltage.

[0005] The above-mentioned inventions have a limitation of only harmonic reduction and controlling a DC-DC converter. Hence a method of reduced power processing LED driver with constant output current has been proposed in the proposed invention. The proposed invention provides an improvement of efficiency in step-down conversion circuits by reducing power processing stages/steps, improvement of power factor with low input current THD as per the standards, elimination of ripple power to prevent the flickering effect on the illumination (light output), the need to replace electrolytic capacitors with long-lifespan capacitors without affecting power density and cost, optimal Power distribution with minimal semiconductor devices and minimal complex control circuits to reduce the cost and size of the driver circuit.

SUMMARY:
[0006] A single-phase LED driver with unidirectional power processing and power decoupling using a split capacitor to reduce power processing has been proposed in the present invention.

[0007] The proposed invention includes two buck-boost converters, wherein one buck-boost converter is used as the two-output power factor correction (PFC) converter with a switch (S1), an inductance (Lpfc), a diode (Da), split capacitors (Co), and (Cdc).

[0008] The other buck-boost converter is used as the power control (PC) converter with a switch (S2), an inductance (Lpc), a diode (Db), and the split capacitor (Cdc).

[0009] The proposed invention is operated in four modes of operation wherein the output capacitor (Co) supplies the load in mode-1. The stored energy in (Lpc) is transmitted to (Co) through (Db) in mode-3. The energy stored in (Lpfc) is transferred to split capacitors (Co) and (Cdc) through (Da) and is completely discharged at t = t3 in mode-3. The split capacitor (Co) maintains the output power in mode-4.

[0010] The efficiency, total harmonic distortion (THD) and power factor (PF) are measured at various output power levels.

OBJECTIVES:
[0011] The main objective of the proposed invention is, enhancement of efficiency in step-down conversion circuits by reducing power processing stages/steps

[0012] The other objective is to enhance power factor with low input current THD.

BRIEF DESCRIPTION OF THE DRAWINGS:
[0013] Figure-1 illustrates the schematic of the proposed LED driver circuit.

[0014] Figure-2 illustrates the modes of operation. (a) Mode I. (b) Mode II. (c) Mode III. (d) Mode IV.

[0015] Figure-3 illustrates the detailed waveforms of operation.

[0016] Figure-4 illustrates the power flow diagram for the proposed topology.

[0017] Figure-5 illustrates the proposed LED driver with ripple cancellation approach.

[0018] Table-1 illustrates the design parameters of a 30 W proposed LED driver.

[0019] Figure-6 illustrates the Input voltage waveform (Vin(t)), ac current waveform (iac(t)), output current waveform (io(t)), output voltage waveform (Vo(t)), and dc bus capacitor voltage (Vdc(t)) waveform.

[0020] Figure-7 illustrates the control signal for (S1) waveform, current (iin(t)) waveform, and current (iLpc(t)) waveform.

[0021] Figure-8 illustrates the control signal for S2 waveform, current (iin(t)) waveform, and current (iLpc(t)) waveform.

[0022] Figure-9 illustrates the current flowing through inductor (Lpfc) is (iLpfc(t)) and inductor (Lpc) is (iLpc(t)).

[0023] Figure-10 illustrates the input voltage waveform (Vin(t)), ac current waveform (iac(t)), output current (io(t)) waveform, and output voltage (Vo(t)) waveform.

[0024] Figure-11 illustrates the input current harmonic spectrum at full power.

[0025] Figure-12 illustrates the THD and PF of the proposed LED driver.

[0026] Figure-13 illustrates the percentage efficiency of the proposed invention.

[0027] Figure-14 illustrates the loss breakdown.

[0028] Table-2 illustrates the comparison of proposed with existing LED driver topologies.

[0029] Figure-15 illustrates at 10 W: input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0030] Figure-16 illustrates at 15 W: input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0031] Figure -17 illustrates at 20 W: input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0032] Figure-18 illustrates at 24 W: input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0033] Figure-19 illustrates at 27 W: input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0034] Figure -20 illustrates at 90 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0035] Figure-21 illustrates at 110 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0036] Figure-22 illustrates at 150 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0037] Figure-23 illustrates at 175 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0038] Figure-24 illustrates at 200 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0039] Figure-25 illustrates at 227 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0040] Figure-26 illustrates at 250 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0041] Figure-27 illustrates at 260 V: dc bus voltage (Vdc(t)), input voltage (Vin(t)), input current (iac(t)), output voltage (Vo(t)), and output current (io(t)).

[0042] Figure-28 illustrates the proposed converter % efficiency and PF with respect to input voltage variation.

[0043] Figure-29 illustrates the block diagram representation of the proposed LED driver topology.

[0044] Figure-30 illustrates the experimental setup.

DETAILED DESCRIPTION OF THE INVENTION:
[0045] A buck-boost converter has been proposed in the present invention to reduce power processing LED driver with constant output current as shown in figure-1. A light emitting diode (LED) driver circuit to enhance high power factor with low total harmonic distortion has been proposed in the present invention. A rectifier which connects the two-output power factor correction (PFC) converter to the input supply (Vin(t)). Two buck-boost converters are used in the proposed invention. The first buck-boost converter is formed with a switch (S1) and an inductance (Lpfc) connected in parallel to a diode (Da), split capacitors ((Co), (Cdc)). The split capacitors (Co) and LED load are connected in parallel. The first buck-boost converter used as a two-output power factor correction (PFC) converter. The second buck-boost converter is formed with an inductance (Lpc), a diode (Db), and the split capacitor (Cdc) connected in parallel to a switch (S2). The second buck-boost converter used as a power control (PC) converter. The power control (PC) converter output is connected in series to the LED load.

[0046] The split capacitor (Cdc) acts as the input to the power control (PC) converter. The two-output power factor correction (PFC) converter is connected in series to the power control (PC) converter. The rectifier is connected to the two-output power factor correction (PFC) converter and the power control (PC) converter whereby forms a LED driver circuit. A plurality of modes of operation are conducted with the LED driver circuit. The switch (S1) of the two-output power factor correction (PFC) converter and the switch (S2) of the power control (PC) converter are turned on in mode-1 at t = to. The inductor (Lpfc) of the two-output power factor correction (PFC) converter is charged by the input supply (Vin(t)). The inductor (Lpc) of the power control (PC) converter is charged through the voltage (Vdc). The split capacitor (Co) supplies the LED load. The switch (S1) of the two-output power factor correction (PFC) converter is turned on and the switch (S2) of the power control (PC) converter is turned off in mode-2 at t=t1.

[0047] The energy is stored in inductor (Lpc) of the power control (PC) converter and the inductor (Lpc) of the power control (PC) converter transmits stored energy to the split capacitor (Co) through the diode (Db). The switch (S1) of the two-output power factor correction (PFC) converter is turned off and the switch (S2) of the power control (PC) converter is turned on in mode-3 at t=t2. The energy is stored in inductor (Lpfc) which is transmitted to the split capacitors (Co) and (Cdc) through the diode (Db) with the input current during t0≤t≤t2 being proportional to the input voltage (Vin(t)), ensuring the current shape aligns with the voltage. The switches (S1), (S2) of the two-output power factor correction (PFC) converter and the power control (PC) converter are turned off and diodes (Da), (Db) are turned off in mode-4. The split capacitor (Co) maintains the output power. A ripple cancellation approach which eliminates ripple in the LED load current has been used in the proposed invention.

[0048] The harmonic distortion is reduced by the smoothing action of the inductor ((Lpfc), (Lpc)) and split capacitors ((Co), (Cdc)). The split capacitors ((Co), (Cdc)) aids in minimizing ripples in both current and voltage. The two output power Popfc (t) is split into direct power (Pd(t)) and reprocessed power (Pr(t)) using the voltage across the split capacitors ((Co), (Cdc)). The direct power (Pd(t)) is sent directly to the LED load and the reprocessed power (Pr(t)) is processed through the power control (PC) converter. The ripple is effectively cancelled out, ensuring the LED load receives a smooth and steady current. The power control (PC) converter reshapes the ripple power transforming into a stable, constant output power. The ripple cancellation approach aids in enhancing the overall performance of the LED driver circuit.

[0049] The maximum amount of direct power (Pd(t)) delivered to the load is half of the total output power of the power factor correction (PFC) converter (Popfc(t)). The remaining half of the power (Pr(t)) is sent to the load through a (PC) converter. The PC converter converts (Pr(t)) into cancellation power (Pc(t)). The output power is the sum of direct power (Pd(t)) and cancellation power (Pc(t)). The phase difference between (Pd(t)) and (Pc(t)) is 180° out of phase to maintain constant DC output power. Since, the power control (PC) converter uses only half of the total power, its cost and size are minimized. despite the fact that the design has two converters with separate controllers, It can be categorized as single-stage because 50% of the power is supplied to the load directly, and only the remaining 50% is processed by the (PC) converter.

[0050] The two-output power factor correction (PFC) converter stage operates in discontinuous conduction mode (DCM) to obtain a high PF. The buck-boost converter was used as the power control (PC) converter due to its simplest non-isolated design with a negative input terminal operating as a positive output terminal. The buck-boost converter's voltage-follower capabilities in discontinuous conduction mode (DCM) simplify the control stage. The proposed converter has four operational modes as shown in figure-2. Figure-3 depicts the operating modes of the converter waveforms.

P_in (t)=V_in (t) i_in (t)=V_m sin⁡ωt×I_m sin⁡ωt (1)

P_in (t)=P_o (1-cos⁡2ωt ) (2)

[0051] A plurality of modes of operation. The switches (S1) and (S2) are turned on in mode-1 (t0 < t < t1) at t = to. The inductor (Lpfc) is charged by the (Vin(t)), and the inductor (Lpc) is charged through the voltage (Vdc) simultaneously as shown in figure-2 (a). The energy is stored in inductor (Lpc) which is transmitted to capacitor (Co) through the diode (Db) as shown in figure-2(b). The energy is stored in inductor (Lpfc) which is transmitted to the capacitors (Co) and (Cdc) through the diode (Db) as shown in figure-2(c). Since the input current is equal to the inductor (Lpfc) current up to (t0 < t ≤ t2) and zero in all other modes. Therefore, the peak input current is written as
i_inpk (t)=(V_m |sin⁡ωt | d_1)/(L_pfc f_sw ) (3)

where f_swis the switching frequency and d1 is the duty cycle for switch (S1). For a switching period, the average input current is

i_inav (t)=(V_m |sin⁡ωt | d_1^2)/(〖2L〗_pfc f_sw ) (4)

[0052] From (4), since the input voltage and current are proportional, a constant duty ratio may naturally achieve power factor correction (PFC) converter. The proposed invention achieves a high-power factor (PF) with reduced AC side harmonics and flicker-free DC side operation through several vital mechanisms. Operating in Discontinuous Conduction Mode (DCM), the inductor current is fully depleted by the end of each switching cycle, ensuring that the input current remains proportional to the input voltage during the cycle. This creates a current waveform closely following the sinusoidal input voltage, reducing phase differences and improving PF. In mode 3, when switch S1 is turned off, the energy stored in the inductor (Lpfc) is transferred to output split capacitors (Co) and (Cdc) via diode (Da), with the input current during t0≤t≤t2 being proportional to the input voltage, ensuring the current shape aligns with the voltage.

[0053] Harmonic distortion is reduced by the smoothing action of the inductor and capacitors, which help minimize ripples in both current and voltage. Since the DCM operation ensures the inductor current drops to zero before the next cycle begins, this prevents reverse current flow and higher-order harmonics, resulting in a cleaner current. Using a high switching frequency (fsw) further improves converter performance by reducing harmonics. A constant or optimized duty cycle keeps the input voltage and current proportional, which enhances power conversion efficiency and reduces reactive power.

The average input power is obtained as follows:


P_o=1/(T_line/2) ∫_0^(T_time/2)▒〖V_m |sin⁡ωt | i_inav (t)dt 〗 (5)

By substituting (5) into (6) yields

P_o=(V_m^2 d_1^2)/(4L_pfc f_sw ) (6)

d_1=2/V_m √(P_in L_pfc f_sw ) (7)

i_inpk (t)=2√(P_in/(L_pfc f_sw )) |sin⁡ωt | (8)

Mode-4 (t3 < t < Ts): In this mode, all the switches and diodes are turned off, and the split capacitor (Co) maintains the output power as shown in Fig. 2(d).

[0054] Power Decoupling: Based on the voltages across the split capacitors (Co) and (Cdc), (Popfc(t)) is split into two portions [(Pd(t)) and (Pr(t))]. The following expressions are obtained. The factor of reprocessing power 'a' can be defined as
a=(P_r (t))/(P_d (t)+P_r (t)) (9)


a=V_dc/(V_o+V_dc )=1/(1+K) (10)

where K is the voltage ratio
K=V_o/V_dc (11)

〖P 〗_d (t)=V_o i_opfc (t) (12)

and
〖P 〗_r (t)=V_dc i_opfc (t) (13)

The current flowing through the series connected capacitors (i_opfc (t)) can be estimated as

i_opfc (t)=(P_opfc (t))/(V_o+V_dc ) (14)

Substituting (15) into (13) and (14), then
P_d (t)=V_o (P_opfc (t))/(V_o+V_dc ) (15)

P_r (t)=V_dc (P_opfc (t))/(V_o+V_dc ) (16)

Substituting (13) into (17) and (18), then

P_d (t)=K/(1+K) P_opfc (t) (17)

P_r (t)=1/(1+K) P_opfc (t) (18)

P_d (t)=K/(1+K) 〖2P〗_o 〖sin〗^2 (ωt) (19)

P_r (t)=1/(1+K) 〖2P〗_o 〖sin〗^2 (ωt) (20)

max P_r (t)=〖2P〗_o/(1+K) (21)

[0055] According to the above analysis, figure-1 depicts the proposed topology operating with the two-output power factor correction (PFC) converters which achieves power distribution without the use of the additional switch and diode, resulting in low cost and high-power density.
The sum of 〖(P〗_d (t))and 〖(P〗_c (t)) is the constant output power.

P_c (t)=P_o-P_d (t) (22)

P_c (t)=P_o-K/(1+K) 〖2P〗_o 〖sin〗^2 (ωt) (23)

(P_c (t))is created by (PC) converter. Substituting 〖sin〗^2 (ωt)=1-cos2ωt


P_c (t)=P_o (1-K)/(1+K)-K/(1+K) 〖2P〗_o 〖sin〗^2 (ωt) (24)

[0056] Using a simple ripple cancellation control approach, the proposed invention eliminates the 100 Hz ripple in the LED load current. The design involves splitting the output power of the (PFC) converter into two parts using two capacitors. The total 100 Hz ripple power is divided into these two portions. One portion of the power is sent directly to the LED load, while the other portion is processed through a secondary converter. This secondary converter reshapes the 100 Hz ripple power, transforming it into a stable, constant output power. By doing so, the ripple is effectively canceled out, ensuring that the LED load receives a smooth and steady current. This approach minimizes flicker and maintains consistent light output, enhancing the overall performance of the LED driver.

[0057] To produce required cancellation power 〖(P〗_c (t)) required to cancel the ripple on the output power the voltage ratio K is selected wherein K must be equal to one. When the power losses in the reprocessing state are considered, K must be

K≤1 (25)

P_o=P_d (t)+P_c (t)=P_o 〖sin〗^2 (ωt) +P_o 〖cos〗^2 (ωt)=P_o (26)

The voltage gain of the PFC converter is

V_gpfc=(V_o+V_dc)/V_in (27)

The voltage gain of the PC converter is

V_gpfc=V_o/V_dc =K (28)

The total voltage gain of the driver circuit is

V_g=V_o/V_in =(V_gpfc V_gpc)/(1+V_gpc )=(V_gpfc K)/(1+K) (29)

[0058] The total input power is processed through the (PFC) converter and then it is split into two portions based on the value "a". The "a" times input power sent to the storage capacitor and the remaining power, (1-a) times input power, sent directly to the load. The overall η of the driver can be estimated as

ƞ=aƞ_1 ƞ_2+(1-a) ƞ_1 (30)

where 1 and 2 are the PFC and PC converter efficiencies, respectively.

Substituting (12) into (32)
ƞ=1/(1+K) ƞ_1 ƞ_2+(1-1/(1+K)) ƞ_1 ƞ (31)

ƞ=1/(1+K) ƞ_1 ƞ_2+(K/(1+K)) ƞ_1 (32)

ƞ=ƞ_1 (ƞ_2+K)/(1+K) (33)

The voltage ratio K is selected as 0.82 for experimental analysis to requite for the losses in the (PC) converter, the reprocessing power under this condition is 55%.

[0059] DESIGN PROCEDURE: The direct power 〖(P〗_d (t)) should be increased to make this approach more efficient and must below P_o to avoid low-frequency ripples at any time in the output power. Figure-4 depicts the maximum quantity of 〖(P〗_d (t)) is 50% of the input power because the output power is the same as the average input power. The limit condition occurs when both the voltages are equal and only half of the power is reprocessed leading to high efficiency

(34)

[0060] The cost and size of the (PC) converter is less than the second stage of a standard two-stage technique because it handles only half of the total power. The system efficiency increases as more power is transferred to the load. Consequently, compared with the two-stage technique, this allows for the development of smaller and more efficient AC/DC converters. The output voltage of the (PFC) converter is obtained as follows:

i_opfc (t)=(V_m |sin⁡ωt | d_1 (d_1^1-d_1))/(2L_pfc f_sw ) (35)

d_1^1=(〖2i_opfc (t) L_pfc f_sw+V_m |sin⁡ωt |d〗_1^2)/(V_m |sin⁡ωt | d_1 ) (36)

V_dc (t)=(V_m^2 |〖sin〗^2 (ωt)| d_1^2)/(2i_opfc (t)L_pfc f_sw )-V_o (37)

L_pfc (t)=(V_m^2 d_1^2)/(4P_o f_sw ) (38)

The PC converter is operating in DCM. The peak current is

i_Lpcpk (t)=(V_dc d_2)/(L_pc f_sw ) (39)

P_c (t)=(V_dc i_Lpcpk d_2)/2=(V_dc^2 d_2^2)/(2L_pc f_sw ) (40)

L_pc=(〖2P〗_c (t) f_sw)/(V_dc^2 d_2^2 ) (41)

C_dc=(〖2P〗_c (t))/(f_sw ∆V_dc V_dc ) (42)

[0061] CONTROL SCHEME: A ripple cancellation method is used to maintain a constant output current as shown in figure-5. The power distribution becomes simple when the output capacitor of the PFC converter is replaced with two capacitors and requires no change in the switch triggering sequence. A simple control method is sufficient because both converters operate independently. The control variable for achieving PFC is 〖(d〗_1) which directly controls the input power. The input power and output power must be balanced within each line period and the average value of 〖(V〗_dc (t)) must remain constant. The average value of 〖(V〗_dc (t)) is (V_dc). 〖(V〗_dc)is used as a reference to keep 〖(V〗_dc (t)) at the specified value. Figure-5 represents an error signal which is generated by comparing the actual 〖(V〗_dc (t)) with (V_dcref), which is then sent to the PI controller that generates d1 for S1.

[0062] A pulse width modulation (PWM) signal for (S1) is generated using the controller DS1104 DSP. The amount of power required to eliminate ripples in the output can be obtained using control variable (d_2). The average value of the output current (io(t)) is (Io), wherein (Io) is taken as a reference to maintain io(t) constant. Consequently, (Io) is kept constant using (d_2) as a control variable. Figure-5 represents an error signal which is generated by comparing the actual (io(t)) with (Ioref), which is then sent to the PI controller, which generates (d_2). for (S_2), as shown in Fig. 5(b). The DS_1104 controller board is used to generate a PWM signal for S2. The control variable (d_2) always maintains a constant output current throughout each line period.

[0063] Ripple cancellation is a technique used in power electronics to reduce or eliminate unwanted variations, or ripples, in the output voltage or current of a power converter. This process typically involves several steps: first, the total output power is divided into separate portions using multiple capacitors or other energy storage elements. One portion containing the ripple is sent directly to the load, while the other is directed through additional circuitry designed to address and correct the ripple. This secondary processing might include filtering or reshaping the ripple to create a smoother output. The corrected power is then combined with the directly supplied power, resulting in a more stable and consistent output. Feedback mechanisms are often employed to dynamically adjust the ripple cancellation process based on real-time measurements, ensuring that the output remains steady and flicker-free, which is particularly important for applications like LED lighting.

[0064] EXPERIMENTAL RESULTS: An LED driver with a power rating of 30 watts was developed to confirm the viability of the proposed invention design. The specifications for the proposed invention are illustrated in table-1, which includes the AC input current (iac(t)), output current (io(t)), and DC bus capacitor voltage (V_dc (t)) as illustrated in figure-6. The required input current (iac(t)) and constant output current (io(t)) are effectively realized. When switches (S1) and (S2) are activated and both converters PFC and PC operate in the DCM mode, inductors (Lpfc) and (Lpc) are charged. Figure-7 demonstrates the control signal waveform for (S1), current (iin(t)), and current (iLpc(t)). Figure-8 demonstrates the control signal waveform for (S2), current (iin(t)), and current (iLpc(t)).

[0065] As S2 is turned on, inductor (Lpc) is charges, according to theoretical analysis, this occurs when S2 is turned off, the energy stored in (Lpc) is transferred to the capacitor Co through diode Db. Current flowing through inductor (Lpc) is (iLpfc(t)) and inductor (Lpc) is depicted in figure-9. The current through the LED load, (io(t)) and the voltage across the LED load, Vo(t) are illustrated in figure-10. From the above, the output current ripple from peak to peak, is 9% of the average value. Figure-11 depicts the input current harmonic spectrum which shows that lower order harmonics are effectively regulated in accordance with the IEC 61000-3-2 Class C standards. The total harmonic distortion (THD) and power factor (PF) of the proposed circuit is measured at various output power levels as illustrated in figure-12.

[0066] The efficiency of the proposed converter is measured at various output power levels as illustrated in figure-13. The loss breakdown of the proposed invention is depicted in figure-14 which shows that at full power the proposed driver can attain a peak efficiency of 94%. Table II illustrates the comparison of the proposed invention with the existing LED driver topologies. The proposed converter has been tested for various dimming levels and the corresponding waveforms are shown in figures 15-19. Figures 20-27 demonstrates the waveforms for the proposed converter that was tested for universal input voltage. The proposed converter efficiency and power factor with respect to input voltage variation are shown in figure-28. Figures-29 depicts the block diagram representation of the proposed LED driver. The experimental setup of the proposed invention is depicted in figure-30. The LED driver under consideration offers several enhancements are, long lifespan, high power factor, low input current THD, high efficiency, high power density, less cost and size, effectively eliminates 100 Hz ripple, less number switching devices and their complex control circuits, applicable for universal input voltages, applicable for dimming operations for different power levels and simple in design.

[0067] The proposed invention addresses: Improvement of efficiency in step-down conversion circuits by reducing power processing stages/steps, Improvement of power factor with low input current THD as per the standards, Elimination of ripple power to prevent the flickering effect on the illumination (light output), The need to replace electrolytic capacitors with long-lifespan capacitors without affecting power density and cost, Optimal Power distribution with minimal semiconductor devices, Minimal complex control circuits to reduce the cost and size of the driver circuit.
, Claims:CLAIMS:
I/We claim:
1. A light emitting diode (LED) driver circuit to enhance high power factor with low total harmonic distortion, comprising:
a rectifier which connects the two-output power factor correction (PFC) converter to the input supply (Vin(t));
a two buck-boost converters;
wherein the first buck-boost converter is formed with a switch (S1) and an inductance (Lpfc) connected in parallel to a diode (Da), a split capacitors ((Co), (Cdc));
the split capacitors (Co) and LED load are connected in parallel;
whereby the first buck-boost converter used as a two-output power factor correction (PFC) converter;
the second buck-boost converter is formed with an inductance (Lpc), a diode (Db), and the split capacitor (Cdc) connected in parallel to a switch (S2);
whereby the second buck-boost converter used as a power control (PC) converter;
the power control (PC) converter output is connected in series to the LED load;
the split capacitor (Cdc) acts as the input to the power control (PC) converter;
the two-output power factor correction (PFC) converter is connected in series to the power control (PC) converter;
wherein the rectifier is connected to the two-output power factor correction (PFC) converter and the power control (PC) converter;
whereby forms a LED driver circuit;
a plurality of modes of operation;
the switch (S1) of the two-output power factor correction (PFC) converter and the switch (S2) of the power control (PC) converter are turned on in mode-1 at t = to;
wherein the inductor (Lpfc) of the two-output power factor correction (PFC) converter is charged by the input supply (Vin(t));
the inductor (Lpc) of the power control (PC) converter is charged through the voltage (Vdc);
whereby the split capacitor (Co) supplies the LED load;
the switch (S1) of the two-output power factor correction (PFC) converter is turned on and the switch (S2) of the power control (PC) converter is turned off in mode-2 at t=t1;
wherein the energy is stored in inductor (Lpc) of the power control (PC) converter;
whereby the inductor (Lpc) of the power control (PC) converter transmits stored energy to the split capacitor (Co) through the diode (Db);
the switch (S1) of the two-output power factor correction (PFC) converter is turned off and the switch (S2) of the power control (PC) converter is turned on in mode-3 at t=t2;
wherein the energy is stored in inductor (Lpfc) which is transmitted to the split capacitors (Co) and (Cdc) through the diode (Db) with the input current during t0≤t≤t2 being proportional to the input voltage (Vin(t)), ensuring the current shape aligns with the voltage;
the switches (S1), (S2) of the two-output power factor correction (PFC) converter and the power control (PC) converter are turned off and diodes (Da), (Db) are turned off in mode-4;
the split capacitor (Co) maintains the output power;
a ripple cancellation approach which eliminates ripple in the LED load current;
wherein the harmonic distortion is reduced by the smoothing action of the inductor ((Lpfc), (Lpc)) and split capacitors ((Co), (Cdc));
wherein the split capacitors ((Co), (Cdc)) aids in minimizing ripples in both current and voltage;
the two output power Popfc (t) is split into direct power (Pd(t)) and reprocessed power (Pr(t)) using the voltage across the split capacitors ((Co), (Cdc));
the direct power (Pd(t)) is sent directly to the LED load;
whereby the reprocessed power (Pr(t)) is processed through the power control (PC) converter;
wherein the ripple is effectively cancelled out, ensuring the LED load receives a smooth and steady current;
the power control (PC) converter reshapes the ripple power transforming into a stable, constant output power; and
the ripple cancellation approach aids in enhancing the overall performance of the LED driver circuit.
2. The light emitting diode (LED) driver circuit as claimed in claim 1, wherein discontinuous conduction mode operation ensures the inductor current drops to zero before the next cycle begins.
3. The light emitting diode (LED) driver circuit as claimed in claim 1, wherein using a high switching frequency enhances converter performance by reducing harmonics.
4. The light emitting diode (LED) driver circuit as claimed in claim 1, wherein optimized duty cycle keeps the input voltage and current proportional which enhances power conversion efficiency and reduces reactive power whereby enhances a high-power factor (PF).

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