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A NOVEL METHOD OF POWER REDUCTION IN MODIFIED AES USING BIT ENCRYPTION AND DECRYPTION TRANSITION SCHEME ON FPGA
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Abstract
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A NOVEL METHOD OF POWER REDUCTION IN MODIFIED AES USING BIT ENCRYPTION AND DECRYPTION TRANSITION SCHEME ON FPGA
ORDINARY APPLICATION
Published
Filed on 16 February 2021
Patent Information
| Application ID | 202141006425 |
| Date of Application | 16/02/2021 |
Documents
| Name | Date |
|---|---|
| 202141006425-COMPLETE SPECIFICATION [16-02-2021(online)].pdf | 16/02/2021 |
| 202141006425-DECLARATION OF INVENTORSHIP (FORM 5) [16-02-2021(online)].pdf | 16/02/2021 |
| 202141006425-DRAWINGS [16-02-2021(online)].pdf | 16/02/2021 |
| 202141006425-FORM 1 [16-02-2021(online)].pdf | 16/02/2021 |
| 202141006425-FORM-9 [16-02-2021(online)].pdf | 16/02/2021 |
| 202141006425-REQUEST FOR EARLY PUBLICATION(FORM-9) [16-02-2021(online)].pdf | 16/02/2021 |
