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A NOVEL METHOD OF DESIGN OF LOW POWER VLSI BASED VITERBI DECODER USING GATE DIFFUSION INPUT
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A NOVEL METHOD OF DESIGN OF LOW POWER VLSI BASED VITERBI DECODER USING GATE DIFFUSION INPUT
ORDINARY APPLICATION
Published
Filed on 2 February 2021
Patent Information
| Application ID | 202131004459 |
| Date of Application | 02/02/2021 |
Documents
| Name | Date |
|---|---|
| 202131004459-COMPLETE SPECIFICATION [02-02-2021(online)].pdf | 02/02/2021 |
| 202131004459-DECLARATION OF INVENTORSHIP (FORM 5) [02-02-2021(online)].pdf | 02/02/2021 |
| 202131004459-DRAWINGS [02-02-2021(online)].pdf | 02/02/2021 |
| 202131004459-FORM 1 [02-02-2021(online)].pdf | 02/02/2021 |
| 202131004459-FORM-9 [02-02-2021(online)].pdf | 02/02/2021 |
| 202131004459-REQUEST FOR EARLY PUBLICATION(FORM-9) [02-02-2021(online)].pdf | 02/02/2021 |
