A METHOD OF GENERATION OF REGISTER TRANSFER LEVEL (RTL) DESIGN FROM GATE LEVEL NETLIST

Abstract

ABSTRACT A METHOD OF GENERATION OF REGISTER TRANSFER LEVEL (RTL) DESIGN FROM GATE LEVEL NETLIST The present invention discloses a method (100) of generation of RTL design from gate level netlist, comprising forming (102) clusters of standard cells from a technology library by a storage engine (202), generating (104) functionality of the formed cluster in the form of RTL descriptions for each standard cell by the storage engine (202), storing (106) same into a database by the storage engine (202), reading (108) a gate level netlist by a reception engine (204), receiving (110) the netlist by an identification engine (206), receiving (112) the standard cells of the gate level netlist by a co-ordination engine (208) to match standard cells of the gate level netlist with that of cluster database, receiving (114) from the co-ordination engine (208) by a functionality conversion engine (210) to replace the standard cells of the netlist with a functional equivalent RTL design followed by validation by a validation engine (212). {Figure 2 and Figure 6}

Specification

Description:FORM 2
THE PATENTS ACT 1970
39 OF 1970
&
THE PATENT RULES 2003
COMPLETE SPECIFICATION
(SEE SECTIONS 10 & RULE 13)
1. TITLE OF THE INVENTION

"A METHOD OF GENERATION OF REGISTER TRANSFER LEVEL (RTL) DESIGN FROM GATE LEVEL NETLIST"
2. APPLICANTS (S)
NAME NATIONALITY ADDRESS
INDIAN INSTITUTE OF TECHNOLOGY HYDERABAD
An Indian educational Institute Kandi, Sangareddy, Hyderabad, Telangana-502285, India
3. PREAMBLE TO THE DESCRIPTION

COMPLETE SPECIFICATION

The following specification particularly describes the invention and the manner in which it is to be performed.


 
A METHOD OF GENERATION OF REGISTER TRANSFER LEVEL (RTL) DESIGN FROM GATE LEVEL NETLIST
TECHNICAL FIELD
[001] The present disclosure relates to a method of generation of Register Transfer Level (RTL) design from gate level netlist. More particularly, the present disclosure is related to the method of conversion of the gate level netlist to the register transfer level (RTL) design, so that it can be mapped with any technology library for designing a chip.
BACKGROUND
[002] The cost of designing a chip is very costly and it requires huge resource owing to which designers usually rely on integrated circuits (ICs) fabricated in offshore or untrusted foundries. However, such techniques introduce the risk of counterfeit, unreliable, or even malicious modifications to the circuit and therefore requires further verification ensuring that the IC matches identically with the manufacturer's specifications. Additionally, this also involves detecting any malicious or suspicious circuitry within the IC, therefore becomes challenging for a user to handle and manage.
[003] There are two approaches currently being applied for the reverse engineering of the integrated circuit, namely, destructive and non-destructive techniques to generate low level gate circuit design. In destructive approach, the chip's top package is removed and delayered, and each metal layer's image is taken with the help of a Scanning Electronic Microscope (SEM), gate is identified, and analyzed and then original design is recovered in the form of gate level netlist as shown in Figure 1 (a).
[004] Non-destructive technique, on the other hand, is applied before the fabrication of the chip. Herein, the physical layout of the design is converted into the lower-level circuit design (i.e. transistor level) and then transistor level is converted to the gate level netlist as shown in Figure 1 (b).
[005] However, the gate level netlist has limited uses; and therefore in order to make it generic, the gate level netlist is required to be converted to Register Transfer Level (RTL) design. The existing arrangements convert netlist to RTL by searching for register and its input/output lines along with combinational cells followed by storing it in the hash table for an identified pattern to access. This process is followed till the end of the netlist and then finally converted netlist to RTL. There are additional techniques, involving identification of the pattern like the decoder, 2-to-1 mux, adders, Flip Flops, etc., and then, based on the functionality of the identified pattern from the netlist, RTL is generated. But due to an iterative search operation for a register or specific design to match the pattern, both of these approaches are time-consuming and lags in scalability and universality.
[006] Towards this direction, the present invention intends to propose a method for conversion of gate-level netlist to RTL such that the above-mentioned challenges can be circumvented in a cost effective manner.
OBJECTS OF THE INVENTION
[007] Some of the objects of the present disclosure, which at least one embodiment herein satisfy, are listed herein below.
[008] It is an object of the present subject matter to overcome the aforementioned and other drawbacks existing in the prior art systems and methods.
[009] It is a significant object of the present invention to develop a method to convert gate level netlist into RTL.
[010] It is another object of the present invention to develop the method to convert gate level netlist into RTL such that the method applies for any process technology library.
[011] It is another object of the present invention to develop the method to convert gate level netlist into RTL such that the method is applicable for flat as well as the hierarchical netlist.
[012] It is another object of the present invention to develop the method to convert gate level netlist into RTL such that the method is independent of size of the netlist and is applicable for any number of gates in the netlist.
[013] It is another object of the present disclosure to design and develop the method to convert gate level netlist into RTL such that the method is cost effective and simple to implement and faster.
[014] These and other objects and advantages of the present subject matter, will be apparent to a person skilled in the art after consideration of the following detailed description, taken into consideration with accompanied drawings in which preferred embodiments of the present subject matter are illustrated.
SUMMARY OF THE INVENTION
[015] This summary is provided to introduce concepts related to a method of generation of Register Transfer Level Design (RTL) from netlist. The concepts are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
[016] According to an embodiment of the present subject matter, there is provided the method of generation of Register Transfer Level (RTL) design from gate level netlist.
[017] In an aspect, the method comprises forming clusters of a plurality of standard cells from a technology library by a processing unit present in a storage engine, generating functionality of the formed cluster of the plurality of standard cells in the form of Register Transfer Level (RTL) descriptions for each standard cell by the processing unit present in the storage engine, storing the generated functionality into a database by the storage engine, reading a gate level netlist by a reception engine, receiving the netlist by an identification engine, where the identification engine is configured to identify a plurality of components from the netlist, identify one or more standard cells from the plurality of components of the netlist.
[018] In an aspect, the method further includes receiving the one or more standard cells of the gate level netlist by a co-ordination engine, where the co-ordination engine is configured to match one or more standard cells of the gate level netlist with one or more standard cells of cluster database present in the storage engine, receiving information from the co-ordination engine by a functionality conversion engine, where the functionality conversion engine is configured to replace one or more standard cells of the netlist with a functional equivalent register transfer level (RTL) design in order to generate register transfer level (RTL) design of the received netlist and validating the generated register transfer level (RTL) design of against the netlist by a validation engine upon receipt from the functionality conversion engine.
[019] In an aspect, the co-ordination engine matches one or more standard cells of the gate level netlist with one or more standard cells of cluster database in parallel fashion.
[020] In an aspect, the plurality of components identified by the identification engine includes but is not limited to module, primary input, primary output, formation of connecting wires and likes.
[021] In an aspect, one or more standard cells of the netlist includes but is not limited to digital circuits comprising AND configuration, AND-OR-INVERTER (AOI) configuration, sequential circuits and likes.
[022] In an aspect, the validation engine validates the generated register transfer level (RTL) design of the received gate level netlist by determining functionality of the generated register transfer level (RTL) design with respect to a standard netlist present in the storage engine.
[023] In an aspect, the method includes incorporation of a debugging engine, where the debugging engine is configured to receive information from the validation engine in case the generated register transfer level (RTL) design of the received gate level netlist is not correct, determine cause of failure followed by subsequent rectification of the generated register transfer level (RTL) design of the netlist.
[024] In an aspect, the netlist is a synthesized gate level netlist.
[025] In an aspect, the method is independent of size of the gate level netlist.
[026] In an aspect, the method is independent of the technology library being used to form cluster database.
[027] To further understand the characteristics and technical contents of the present subject matter, a description relating thereto will be made with reference to the accompanying drawings. However, the drawings are illustrative only but not used to limit the scope of the present subject matter.
[028] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which numerals represent like components.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWING(S)
[029] It is to be noted, however, that the appended drawings illustrate only typical embodiments of the present subject matter and are therefore not to be considered for limiting of its scope, for the invention may admit to other equally effective embodiments. A detailed description is given with reference to the accompanying figures. In the figures, a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to refer like features and components. Some embodiments of system or methods or structure in accordance with embodiments of the present subject matter are now described, by way of example, and with reference to the accompanying figures, in which
[030] Figure 1 (a-b) illustrates Gate level netlist extraction using destructive and non-destructive approach;
[031] Figure 2 illustrates an exemplary method of generation of Register Transfer Level (RTL) design from gate level netlist and an exemplary components of a system in accordance with an exemplary embodiment of the present disclosure;
[032] Figure 3 depicts an exemplary components of a system executing the proposed method in accordance with an exemplary embodiment of the present disclosure;
[033] Figure 4 depicts an exemplary method of cluster formation of standard cells in accordance with an exemplary embodiment of the present disclosure;
[034] Figure 5 depicts an exemplary method of functionality extraction of standard cells in form of RTL in accordance with an exemplary embodiment of the present disclosure;
[035] Figure 6 illustrates an exemplary detailed flow of method for netlist to RTL conversion in accordance with an exemplary embodiment of the present disclosure; and
[036] Figure 7 depicts an exemplary setup for verification of golden netlist and generated RTL in accordance with an exemplary embodiment of the present disclosure.
[037] The figures depict embodiments of the present subject matter for the purposes of illustration only. A person skilled in the art will easily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.
DETAILED DESCRIPTION
[038] A few aspects of the present disclosure are explained in detail below with reference to the various figures. Example implementations are described to illustrate the disclosed subject matter, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a number of equivalent variations of the various features provided in the description that follows.
[039] While the embodiments of the disclosure are subject to various modifications and alternative forms, specific embodiment thereof have been shown by way of example in the figures and will be described below. It should be understood, however, that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.
[040] The terms "comprises", "comprising", or any other variations thereof used in the disclosure, are intended to cover a non-exclusive inclusion, such that a device, system, assembly that comprises a list of components does not include only those components but may include other components not expressly listed or inherent to such system, or assembly, or device. In other words, one or more elements in a system or device proceeded by "comprises… a" does not, without more constraints, preclude the existence of other elements or additional elements in the system or device.
[041] The present disclosure relates to a method of generation of Register Transfer Level (RTL) design from gate level netlist. The proposed method comprises of database preparation followed by conversion. The database preparation step includes cluster formation of standard cells followed by its RTL generation. After data base formation the proposed methodology is applied to the netlist to generate RTL from the same. The salient features of the proposed method are detailed in subsequent sections.
[042] Figure 2 illustrates an exemplary method (100) of generation of Register Transfer Level (RTL) design from gate level netlist in accordance with an exemplary embodiment of the present disclosure. The order in which the method (100) is described is not intended to be construed as a limitation, and any number of the described method blocks may be combined in any order to implement the method (100), or an alternative method. The work flow of the proposed method (100) is also detailed in Figure 6.
[043] In an aspect, the proposed method (100) is being executed by a system (200), where the system (200), as shown in Figure 3, may comprise a storage engine (202), a reception engine (204), an identification engine (206), a co-ordination engine (208), a functionality conversion engine (210), a validation engine (212) and a debugging engine (214).
[044] In an aspect, at block (102), the method (100) includes forming clusters of a plurality of standard cells from a technology library by a processing unit present in the storage engine (202). The technology library may comprise of standard cells which includes but is not limited to AN2D0 (AND cell), AOI2D0 (AND-OR-INVERT cell), OA2D0 (OR-AND cell), DFD1 (D-flip Flop cell), etc. Additionally, there may also be numerous variants of the plurality of standard cells, each with a different driving strength and input configuration.
[045] At block (104), the method (100) includes generating functionality of the formed cluster of the plurality of standard cells in the form of Register Transfer Level (RTL) descriptions for each standard cell by the processing unit present in the storage engine (202).
[046] At block (106), the method (100) includes storing the generated functionality into a database by the storage engine (202).
[047] At block (108), the method (100) includes reading a gate level netlist by the reception engine (204).
[048] At block (110), the method (100) includes receiving the netlist by an identification engine (206). In an aspect, the identification engine (206) further is configured to identify a plurality of components from the netlist followed by identification of one or more standard cells from the plurality of components of the netlist.
[049] In an aspect, the plurality of components identified by the identification engine (206) includes but is not limited to module, primary input, primary output, formation of connecting wires and likes.
[050] At block (112), the method (100) includes receiving the one or more standard cells of the gate level netlist by the co-ordination engine (208). Herein, the co-ordination engine (208) is configured to match one or more standard cells of the gate level netlist with one or more standard cells of cluster database present in the storage engine (202).
[051] At block (114), the method (100) includes validating the generated register transfer level (RTL) design against the netlist by the validation engine (212) upon receipt of information from the functionality conversion engine (210). Herein, the validation engine (212) validates the generated register transfer level (RTL) design of the received gate level netlist by determining functionality of the generated register transfer level (RTL) design with respect to a standard netlist present in the storage engine (202).
[052] In an aspect, further, the method (100) includes the debugging engine (214), with the debugging engine (214) being configured to receive (118-1) information from the validation engine (212) in case the generated register transfer level (RTL) design of the received gate level netlist is not correct. This is followed by determining (118-2) the cause of failure along with subsequent rectification of the generated register transfer level (RTL) design of the netlist.
[053] In an aspect, the co-ordination engine (208) is configured to match one or more standard cells of the gate level netlist with one or more standard cells of cluster database in parallel fashion.
[054] In an aspect, it may be mentioned that one or more standard cells of the netlist includes but is not limited to digital circuits comprising AND configuration, AND-OR-INVERTER (AOI) configuration, sequential circuits and likes.
[055] In an aspect, the netlist is synthesized gate level netlist. Moreover, the method (100) is independent of the size of the gate level netlist and also independent of the technology library being used to form cluster database.
[056] Figure 4 depicts an exemplary method of cluster formation of standard cells in accordance with an exemplary embodiment of the present disclosure.
[057] In an aspect, each cell of the plurality of standard cells are clustered in various groups, such as all AND-type standard cells in the AND group, all AOI cells in the AOI group, and all FF in the sequential group.
[058] For example, say, a complete technology library comprises of 'n' number of standard cells and 'k' type of standard cells. Let's consider 'L' as a technology node. It can vary for different foundries. Cluster generation is illustrated as, {n}, {k} ϵ L, where n > 0, k ≥ 1 and {k} ϵ n, where 'k' is the number of clusters.
[059] In an aspect, the same process is further applied for all technology nodes for cluster formation and grouped in 'k'. Therefore, there are nine AOI standard cells in 90nm technology, and all are clustered in one group as shown in Figure 4.
[060] Figure 5 depicts an exemplary method of functionality extraction of standard cells in form of RTL in accordance with an exemplary embodiment of the present disclosure. In a preferred embodiment, the RTL is synthesized with TSMC library tcbn45gsbwplt.db, tcbn65gplusbc.db, tcbn90ghpbc_ccs.db from 45nm ,65nm and 90nm respectively. The AOI cell used in the netlist are AOI21D0BWP, AOI21D0 and AOI21D0 from 45nm, 65nm and 90nm respectively and therefore one RTL of standard cells has been mapped with each of the AOI cell. In this way the cluster database is made from different technology node from TSMC. After clustering formation, functionality is extracted in the form of RTL corresponding to each standard cell from the library datebook mapped to the standard cell name and stored in the database.
[061] Additionally, in a preferred embodiment, functionality may also be extracted from the process library. Basics standard and combinational cell's functionality are extracted in structural or data flow modelling style.
[062] For example, let there be two cells, say, AOI22D0 and DFCNQD1 cells whose functionality are extracted. AOI22D0 is an AND-OR-INVERT cell that has four inputs and one output. Inputs N3070 and n2334 are connected with the one AND gate and N959 and n2330 are connected with other AND gate and output of these two AND gate is connected with NOR gate. The AND gate output is declared as wire a401 and a402, and the final RTL is generated as shown to the cell. DFCNQD1 is a D Flip-Flop with single output Q, whose functionality is extracted at the behavioral level as illustrated in Figure 5. Similarly, the functionality of all standard cells are extracted and mapped to each standard cell name to make a database. After making the database of all standard cells netlist to RTL conversion is being performed.
[063] Figure 7 depicts an exemplary setup for verification of golden netlist and generated RTL in accordance with an exemplary embodiment of the present disclosure.
[064] In a preferred embodiment, for the purpose of verification, a test bench is written by means of the validation engine (208) that can generate stimulus pattern which is fed to golden (or predefined standard) netlist and generated RTL. The same pattern is being fed to golden netlist and generated RTL and output is observed. If the functionality of golden netlist and generated RTL is matched during functional verification, then the generated RTL is correct, and if mismatched, then the generated RTL is incorrect.
[065] In an aspect, further if the generated RTL is found to be incorrect, the generated RTL is analyzed and debugged by the debugging engine (214) till the correct RTL is generated.
[066] In an aspect, the generated RTL is synthesizable and can be further used in any IC design. Moreover, as already mentioned, the proposed method (100) as disclosed in the present disclosure can be further scalable to any process technology.
Test Results
[067] The proposed method (100) as disclosed in the present disclosure has been tested on different circuits of benchmark suit viz., ISCAS-85, ITC-99, PicoRV32 processors, and AI accelerator for validation. It has been observed that the proposed method generates the correct RTL.
[068] Further, the RTL has been generated from netlist synthesized with different technology, and it was observed that the generated RTL matches with the functionality of golden netlist, thereby confirming on generic nature of the proposed method (100). Logical equivalence also ensures that the generated RTL is identical to gate level netlist. Further, the proposed method (100) has been evaluated on flat as well as hierarchical netlists and it has been found that the method (100) works well for both scenarios.
[069] In the present disclosure, the storage engine (202), the reception engine (204), the identification engine (206), the co-ordination engine (208), the functionality conversion engine (210), the validation engine (212) and the debugging engine (214) executing the method (100) comprises of one or more processor(s) to execute the proposed method (100). The processor(s) may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, logic circuitries, and/or any devices that manipulate data based on operational instructions. Among other capabilities, the one or more processor(s) are configured to fetch and execute computer-readable instructions stored in the memory of the system (200). The memory may store one or more computer-readable instructions or routines, which may be fetched and executed to create or share data units over a network. The memory may include any non-transitory storage device including, for example, volatile memory such as RAM, or non-volatile memory such as EPROM, flash memory, and the like.
[070] In an aspect, there may also be provided a variety of interface(s) (216), for example, interfaces for data input and output device/s referred to as I/O devices, interfaces for communication device, storage devices, user interfaces and the like. The interface(s) may facilitate communication between different engines viz., the storage engine (202), the reception engine (204), the identification engine (206), the co-ordination engine (208), the functionality conversion engine (210), the validation engine (212) and the debugging engine (214). The interface(s) may also provide a communication pathway for one or more components of the system (200) while the proposed method (100) is executed. Examples of such components include, but are not limited to, processing device(s) (218) and data storage. Further there is also provided data storage (220) facility.
[071] Herein, the processing devices(s) (218) may be implemented as a combination of hardware and programming device(s) (for example, programmable instructions) to implement one or more functionalities of the processing device(s) (218). In examples described herein, such combinations of hardware and programming may be implemented in several different ways. In one example, the programming for the processing device(s) (218) may be processor executable instructions stored on a non-transitory machine-readable storage medium and the hardware for the processing device(s) (218) may include a processing resource (for example, one or more processors), to execute such instructions. In other examples, the processing devices(s) (218) may be implemented by electronic circuitry.
[072] Technical Advantages
All in all, the method (100) proposed in the present invention is having the following advantages:
i) Facilitates generation of RTL from the physical layout
ii) Facilitates verification of the functionality to detect malwares possibly inserted at the physical layout by an untrusted back-end designer
iii) Beneficial to the reverse engineers by enabling them to extract the netlist followed by conversion of the netlist to RTL
iv) Simple and easy to implement
v) Cost effective
Equivalents
[073] It should be noted that the description and figures merely illustrate the principles of the present subject matter. It should be appreciated by those skilled in the art that conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present subject matter. It should also be appreciated by those skilled in the art that by devising various systems that, although not explicitly described or shown herein, embody the principles of the present subject matter and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the present subject matter and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. The novel features which are believed to be characteristic of the present subject matter, both as to its organization and method of operation, together with further objects and advantages will be better understood from the above-mentioned description when considered in connection with the accompanying figures.
[074] Although embodiments for the present subject matter have been described in language specific to package features, it is to be understood that the present subject matter is not necessarily limited to the specific features described. Rather, the specific features and methods are disclosed as embodiments for the present subject matter. Numerous modifications and adaptations of the system/device of the present invention will be apparent to those skilled in the art, and thus it is intended by the appended claims to cover all such modifications and adaptations which fall within the scope of the present subject matter.
[075] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances, where a convention analogous to "at least one of A, B, or C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."
[076] It will be further appreciated that functions or structures of a plurality of components or steps may be combined into a single component or step, or the functions or structures of one-step or component may be split among plural steps or components. The present invention contemplates all these combinations. Unless stated otherwise, dimensions and geometries of the various structures depicted herein are not intended to be restrictive of the invention, and other dimensions or geometries are possible. In addition, while a feature of the present invention may have been described in the context of only one of the illustrated embodiments, such feature may be combined with one or more other features of other embodiments, for any given application. It will also be appreciated from the above that the fabrication of the unique structures herein and the operation thereof also constitute methods in accordance with the present invention. The present invention also encompasses intermediate and end products resulting from the practice of the methods herein. The use of "comprising" or "including" also contemplates embodiments that "consist essentially of" or "consist of" the recited feature.












, Claims:We Claim:
1. A method (100) of generation of Register Transfer Level (RTL) design from gate level netlist, the method (100) comprising:
- forming (102) clusters of a plurality of standard cells from a technology library by a processing unit present in a storage engine (202);
- generating (104) functionality of the formed cluster of the plurality of standard cells in the form of Register Transfer Level (RTL) descriptions for each standard cell by the processing unit present in the storage engine (202);
- storing (106) the generated functionality into a database by the storage engine (202);
- reading (108) a gate level netlist by a reception engine (204);
- receiving (110) the netlist by an identification engine (206), wherein the identification engine (206) is configured to:
identify a plurality of components from the netlist,
identify one or more standard cells from the plurality of components of the netlist;
- receiving (112) the one or more standard cells of the gate level netlist by a co-ordination engine (208), wherein the co-ordination engine (208) is configured to match one or more standard cells of the gate level netlist with one or more standard cells of cluster database present in the storage engine (202);
- receiving (114) information from the co-ordination engine (208) by a functionality conversion engine (210), wherein the functionality conversion engine (210) is configured to replace one or more standard cells of the netlist with a functional equivalent register transfer level (RTL) design in order to generate register transfer level (RTL) design of the received netlist; and
- validating (116) the generated register transfer level (RTL) design against the netlist by a validation engine (212) upon receipt from the functionality conversion engine (210).
2. The method (100) as claimed in claim 1, wherein the co-ordination engine (208) matches one or more standard cells of the gate level netlist with one or more standard cells of cluster database in parallel fashion.
3. The method (100) as claimed in claim 1, wherein the plurality of components identified by the identification engine (206) includes but is not limited to module, primary input, primary output, formation of connecting wires and likes.
4. The method (100) as claimed in claim 1, wherein one or more standard cells of the netlist includes but is not limited to digital circuits comprising AND configuration, AND-OR-INVERTER (AOI) configuration, sequential circuits and likes.
5. The method (100) as claimed in claim 1, wherein the validation engine (212) validates the generated register transfer level (RTL) design of the received gate level netlist by determining functionality of the generated register transfer level (RTL) design with respect to a standard netlist present in the storage engine (202).
6. The method (100) as claimed in claim 1, wherein the method (100) includes incorporation of a debugging engine (214), wherein the debugging engine (214) is configured to:
receive (118-1) information from the validation engine (212) in case the generated register transfer level (RTL) design of the received gate level netlist is not correct; and
determine (118-2) cause of failure followed by subsequent rectification of the generated register transfer level (RTL) design of the netlist.
7. The method (100) as claimed in claim 1, wherein the netlist is a synthesized gate level netlist.
8. The method (100) as claimed in claim 1, wherein the method (100) is independent of size of the gate level netlist.
9. The method (100) as claimed in claim 1, wherein the method (100) is independent of the technology library being used to form cluster database.

Dated this 20th day of November, 2024

[SONAL MISHRA]
-DIGITALLY SIGNED-
IN/PA-3929
OF L.S. DAVAR & CO.
ATTORNEY FOR THE APPLICANT(S)

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