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A LOW-LATENCY FPGA FRAMEWORK BASED ON RELIABLE UDP AND TCP RE-ASSEMBLY MIDDLEWARE
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A LOW-LATENCY FPGA FRAMEWORK BASED ON RELIABLE UDP AND TCP RE-ASSEMBLY MIDDLEWARE
ORDINARY APPLICATION
Published
Filed on 19 February 2021
Patent Information
| Application ID | 202121007086 |
| Date of Application | 19/02/2021 |
Documents
| Name | Date |
|---|---|
| 202121007086-ABSTRACT [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-CLAIMS [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-COMPLETE SPECIFICATION [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-CORRESPONDENCE [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-DRAWING [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-FER_SER_REPLY [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-FORM 3 [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-OTHERS [06-12-2022(online)].pdf | 06/12/2022 |
| 202121007086-FER.pdf | 15/09/2022 |
| 202121007086-FORM 3 [15-07-2022(online)].pdf | 15/07/2022 |
| 202121007086-ORIGINAL UR 6(1A) FORM 26-021121.pdf | 05/11/2021 |
| 202121007086-FORM-26 [22-10-2021(online)].pdf | 22/10/2021 |
| Abstract1.jpg | 19/10/2021 |
| 202121007086-Covering Letter [08-07-2021(online)].pdf | 08/07/2021 |
| 202121007086-COMPLETE SPECIFICATION [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-DECLARATION OF INVENTORSHIP (FORM 5) [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-DRAWINGS [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-FIGURE OF ABSTRACT [19-02-2021(online)].jpg | 19/02/2021 |
| 202121007086-FORM 1 [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-FORM 18 [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-PROOF OF RIGHT [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-REQUEST FOR EXAMINATION (FORM-18) [19-02-2021(online)].pdf | 19/02/2021 |
| 202121007086-STATEMENT OF UNDERTAKING (FORM 3) [19-02-2021(online)].pdf | 19/02/2021 |
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