A HIGH-VOLTAGE PULSED POWER GENERATOR PRODUCING MULTIPULSE OUTPUT

Abstract

The present invention pertains to power electronics, specifically to high-voltage solid-state pulsed power generators. Its main emphasis is on the formulation of a novel high-voltage pulsed power generator capable of producing multipulse output. The present invention achieves high voltage gain with fewer energy storage devices and semiconductor switches, thereby improving the generator’s reliability. Further, the present invention offers greater flexibility in adjusting pulse parameters like amplitude, width, and repetition rate, making the generator suitable for a wide range of applications. Additionally, the invention features a modular design that allows for scalability, enabling the addition or removal of its sub-circuits to accommodate varying load demands. Ref. Figure: Figure 1

Specification

Description:FIELD OF INVENTION
The present invention relates to the field of power electronics, more particularly, the invention relates to the high-voltage solid-state pulsed power generators.
The invention primarily focuses on formulation of a new high-voltage pulsed power generator capable of producing multipulse output.

BACKGROUND OF THE INVENTION
Pulsed power generators find applicability in various fields ranging from environmental, medical, defence, and scientific research. One of the industries where these generators are gaining popularity is the food processing industry. Food is a perishable item which suffers spoilage and decay from microbial contamination. The conventional food preservation techniques such as refrigeration, pasteurization at high temperatures, and dehydration cause loss of nutrition, natural taste, and flavor. To retain the nutritional value of the food and lower the processing energy, non-thermal pulsed electric field treatment of food is proposed. The same has been addressed in US Patent no. 5690978 and Canadian Patent no. 2325691. Multiple experiments have confirmed that the application of short-duration high-voltage pulses kill the microorganisms and enzymes responsible for food spoilage. Also, "Effect of electric pulse parameters on releasing metallic particles from stainless steel electrodes during PEF processing of milk," IEEE Trans. Ind. Appl., vol. 50, no. 2, pp. 1402-1409, Mar./Apr. 2014 discussed that the taste and nutritional value of the food undergone PEF treatment remain the same as before.
Further research has confirmed that the high voltage multipulse output increases the effectiveness of the pulsed electric field-based food sterilization process and reduces power consumption. The multipulse waveform is obtained by superimposing narrow pulses on wide pulses. The wider pulses may cause a continuous breakdown in the air, which as a result, puts the requirement for a more powerful pulsed power generator. However, narrow pulses may avoid the breakdown of the air, but is not effective for the sterilization process. Therefore, to mitigate this problem, the concept of multipulse is introduced to meet the requirements of the food processing industries. Some of the high voltage multipulse generators reported so far are discussed below.
"Analysis and design of a soft switching interleaved forward converter for generating pulsed electric field," in Proc. 25th Int. Telecommun. Energy Conf., pp. 705-712, Oct. 2003, proposed a new soft-switching converter for microbe sterilization applications. The proposed multipulse generator is derived from the interleaved forward converter and uses an additional filter inductor. This makes the generator bulky and heavy.
"Wide pulse combined with narrow-pulse generator for food sterilization," IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 741-748, Feb. 2008, proposed a mulipulse generator for solid food sterilization. The proposed generator is synthesized by combining a high step-up forward converter, a narrow pulse generator, and a full-bridge inverter. The wide pulses generated by the forward converter are combined with the narrow-pulsed output of the narrow pulse inverter to produce the multipulse output. The proposed generator reduces power consumption, but its inverter's switches must withstand the voltage stress equal to the magnitude of the pulsed output.
A new pulsed power supply for the generation of high-voltage multipulse waveform is presented in "High-voltage pulsed power supply to generate wide pulses combined with narrow pulses," IEEE Trans. Plasma Sci., vol. 42, no. 7, pp. 1894-1901, Jul. 2014. The topology is a combination of a conventional capacitor-diode voltage multiplier and the resonant circuit. It can generate the pulsed output at high voltage-gains because it charges its capacitors in such a way that the capacitors at the higher stage have the higher voltage. However, the maximum voltage up to which the higher stage capacitors can be charged is subject to the availability of the power-electronics switches and passive devices in those ratings.
For the above-mentioned reasons, which will be understood by those skilled in the art upon reading the specification, there is a need in the art for a system for high voltage pulsed power generator that is modular, scalable, produces multipulse output, generates high voltage gain, provides flexibility in the adjustment of the pulsed output, and uses a smaller number of switches and capacitors.

OBJECTIVES OF THE INVENTION
The major objective of this invention is to formulate a high voltage pulsed power generator capable of producing multipulse output. Further, the present invention achieves a high voltage gain with lesser number of energy storage devices and semiconductor switches, thereby enhancing the reliability of the generator. The present invention provides more degree of freedom in the adjustment of pulse parameters such as amplitude, width, and repetition rate. Thus, enabling the generator to find suitability in a wide variety of applications. Furthermore, the present invention has a modular structure and offers scalability, where its sub-circuits can be added or removed to meet the changed load demands.

SUMMARY OF THE INVENTION
This summary offers an introduction to a set of concepts in a simplified format, which are further explained in the detailed description of the invention. The accompanying drawings show only typical embodiments of the invention and thus are not to be considered limiting of its scope.
The present subject matter pertains a high voltage solid-state pulsed power generator, which is given the name HVMG. HVMG stands for high voltage multipulse generator. The system consists of a dc voltage source (VS), a main switch (TS), a load switch (TP4), and multiple sub-modules (SM) and sub-stages (SS). The switch herein refers to a controllable switch like MOSFET or an IGBT with anti-parallel diode. A sub-module consists of a capacitor, a resistor, and two switches, whereas a sub-stage consists of a capacitor, a diode, and three switches. The invention is further described by considering that the generator comprises of two sub-modules and three sub-stages. It is done to make the simpler representation for easier understanding of the concept and not to restrict the number of sub-modules and sub-stages employed in the generator. Further, a generator can have multiple sub-modules and sub-stages depending on the need of the application, device's availability, and user's conscience.
The system as illustrated in the accompanying drawings is built by connecting the sub-modules in series and then connecting the new formation in parallel with a cascaded structure formed by connecting the sub-stages in parallel. A sub-module is formed by connecting one terminal of the capacitor, CSM1 to the collector of T1a through a resistor, rlimit. Emitter of T1a is further connected to the collector of T1b, whose emitter is connected to the other terminal of CSM1. In the same manner, the other sub-module is also built. To connect the sub-modules in series emitters of T1b and T2a are connected. If more number of sub-modules need to be employed, they can be inserted in between the two sub-modules depicted in the accompanying drawing.
A sub-stage is developed by connecting anode of a diode, D (e.g. D1, D2, D3), with collector of TP (e.g. TP1, TP2, TP3), whose emitter is further connected with collector of TC (e.g. TC1, TC2, TC3), and one terminal of the capacitor, CSS, (e.g. CSS1, CSS2, CSS3), whose other terminal is connected with cathode of the diode of the same sub-stage. Sub-stages are connected in parallel to build the system, herein to connect them in parallel, cathode of the diode and collector of TC of the initial stage is connected with the anode of the diode and emitter of TC of the next immediate stage, respectively.
Further to build the complete system, the positive side of VS is connected to the collector of TS, whose emitter is connected to the emitter of T1a, anode of D1, and collectors of T1b and TP1. Further, the sub-modules are connected in series as explained above and the emitter of T2b is connected with the emitter of TC1 and the negative terminal of VS, which is also the ground for the system. All the sub-stages are then connected together in parallel. Furthermore, the load switch, herein, TP4 is connected between the cathode of the diode (herein, D3) of the last stage and the resistive load, R, whose other terminal is connected with the ground.
The above description is made by considering the solid-state switches to be IGBTs with anti-parallel diode. If the MOSFETs are utilized in place of IGBTs, then in the above statements, collector and emitter of the switches to be read as drain and source, respectively. Further, an external diode can be connected across the IGBT if it does not have an internal anti-parallel diode. An in-depth study on the principle and working of the pulsed power generator is provided in the detailed description of the invention.

BRIEF DESCRIPTION OF DRAWINGS
It is to be noted, however, that the appended drawings illustrate only typical embodiments of the present subject matter and are therefore not to be considered for limiting of its scope, for the disclosure may admit to other equally effective embodiments.
Figure 1 illustrates a schematic circuit diagram of the high voltage multipulse generator (HVMG) consisting of two sub-modules (SM) and three sub-stages (SS).
Figure 2(a) illustrates an equivalent circuit diagram in mode-1 of the proposed HVMG consisting of two SM and three SS.
Figure 2(b) illustrates an equivalent circuit diagram in mode-2 of the proposed HVMG consisting of two SM and three SS.
Figure 2(c) illustrates an equivalent circuit diagram in mode-3 of the proposed HVMG consisting of two SM and three SS.
Figure 2(d) illustrates an equivalent circuit diagram in mode-4 of the proposed HVMG consisting of two SM and three SS.
Figure 3 illustrates the switching pattern and all key voltage waveforms of HVMG consisting of two SM and three SS.
Figure 4 illustrates the switching arrangement during a sub-mode of mode-4 to generate a wider part of the high voltage multipulse through an HVMG consisting of two SM and three SS.
Figure 5 illustrates the waveform of the dc source voltage (VS) and the pulsed output voltage (VPulse) generated by the HVMG.
Figure 6 illustrates the voltage waveform of both the SM capacitors (VCSM1 and VCSM2) along with the third SS capacitor (VCSS3) and the pulsed output voltage (VPulse).
Figure 7 illustrates the voltage waveform of all the three SS capacitors (VCSS1, VCSS2, and VCSS3) along with the pulsed output voltage (VPulse).
Figure 8 illustrates the waveforms of the source voltage (VS) along with the 20 µs wide output pulse (VPulse) repeating at a rate of 2 kHz.
Figure 9 illustrates 80 µs wide multipulse waveform (VPulse) along with the source voltage (VS).
These and other features and advantages of the present invention will become fully apparent from the following detailed description and claims of the presently preferred aspects with reference to the appended drawings.

DETAILED DESCRIPTION OF THE INVENTION
It will be apparent to those skilled in the art that various alterations and modifications may be made to the described embodiments without departing from the scope of the invention. Furthermore, the details of well-known functions and structures have been excluded to ensure clarity and brevity.
The singular terms, "a," "an," and "the" also encompass their plural forms, unless the context explicitly indicates otherwise.
It is important to note that the term "comprises/comprising," as used in this specification, is intended to indicate the inclusion of specified features, integers, steps, or components, but does not exclude the possibility of one or more additional features, steps, components, or groups being present or added.
To provide ease in understanding of the concept, the invention is discussed by considering that the embodiment comprises of two sub-modules and three sub-stages. It is not intended to limit the number of sub-modules and sub-stages employed in the generator. A generator can have multiple sub-modules and sub-stages depending on the need of the application, device's availability, and user's conscience.
Features described and/or illustrated in relation to one embodiment may be applied similarly in one or more other embodiments, either independently or in combination with, or as a substitute for, the features of those other embodiments.
The terms and language in the following description and claims are not confined to their standard definitions but are employed to facilitate a clear and coherent understanding of the invention. Therefore, it should be evident to those skilled in the art that the description of exemplary embodiments provided herein is for illustrative purposes only and is not intended to limit the scope of the invention.
Figure 1 illustrates a schematic circuit diagram of the high voltage multipulse generator (HVMG) consisting of two sub-modules (SM) and three sub-stages (SS). The generator shown here consists of a dc voltage source (VS), a main switch (TS), a load switch (TP4), and multiple sub-modules (SM) and sub-stages (SS). A sub-module consists of a capacitor, a resistor, and two switches, whereas a sub-stage consists of a capacitor, a diode, and three switches. The switch herein refers to a controllable switch like MOSFET or an IGBT with anti-parallel diode. Further, an external diode can be connected across the IGBT if it does not have an internal anti-parallel diode.
The system as illustrated in Figure 1 is built by connecting the two sub-modules in series and then connecting the new formation in parallel with a cascaded structure formed by connecting three sub-stages in parallel. A sub-module is formed by connecting one terminal of the capacitor, CSM1 to the collector of T1a through a resistor, rlimit. Emitter of T1a is further connected to the collector of T1b, whose emitter is connected to the other terminal of CSM1. Similarly, the other sub-module is also designed. To connect the sub-modules in series emitters of T1b and T2a are connected. If more number of sub-modules need to be employed, they can be inserted in between the two sub-modules depicted in the accompanying drawing.
A sub-stage is developed by connecting the anode of a diode, D (e.g. D1, D2, D3), with the collector of TP (e.g. TP1, TP2, TP3), whose emitter is further connected with collector of TC (e.g. TC1, TC2, TC3), and one terminal of the capacitor, CSS, (e.g. CSS1, CSS2, CSS3). The other terminal of CSS is connected with diode's cathode of the same sub-stage. To connect the sub-stages in parallel, diode's cathode and TC switch's collector of the initial stage is connected with the diode's anode and TC's emitter of the next immediate stage, respectively.
Further to build the complete system, the positive side of VS is connected to the collector of TS, whose emitter is connected to the emitter of T1a, anode of D1, and collectors of T1b and TP1. Further, the sub-modules are connected in series as explained above and the emitter of T2b is connected with the emitter of TC1 and the negative terminal of VS, which is also the ground for the system. All the sub-stages are then connected together in parallel. Furthermore, the load switch, herein, TP4 is connected between the cathode of the diode (herein, D3) of the last stage and the resistive load, R, whose other terminal is connected with the ground.
The above description is made by considering the solid-state switches to be IGBTs with anti-parallel diode. If the MOSFETs are utilized in place of IGBTs, then in the above statements, collector and emitter of the switches to be read as drain and source, respectively.
HVMG has a simple working principle in which the source voltage, VS, first charges the storage capacitors of all SM one by one at the source voltage levels. Then, the SM capacitors are used for charging the storage capacitors of SS at an enhanced voltage (in multiples of the source voltage's magnitude). When all the SS capacitors are charged to their steady-state voltage levels, they and all the SM capacitors are connected in series with the load to produce a high-voltage pulse discharge. HVMG consisting of two SM and three SS has the following four modes of operation:
Mode-1: The equivalent circuit diagram of HVMG during mode-1 is illustrated in Figure 2(a). The capacitor of the first SM gets charged in this mode. It is done by turning ON, TS and T2b switches. T1a, T2a, T1b, and TP4 along with the switches of all SS are turned OFF. This switching arrangement makes the antiparallel diode of the switch T1a conduct and provides the path for charging the capacitor, CSM1. The other capacitors of the HVMG are disconnected from both the source and the load. By the end of this mode, CSM1 gets charged to VS. A limiting resistor, rlimit is used in the charging path of the SM capacitors to limit the peak inrush current.
Mode-2: This mode has similar operations as the first mode. Figure 2(b) illustrates the equivalent circuit diagram of HVMG during mode-2. The number of these modes depends on the number of SM. Since, we are analyzing an HVMG having two SM and three SS. So, the number of such modes will be one. In this mode, the respective capacitors are charged to VS. The following switching arrangement is utilized in this mode: switch TS remains ON, T1b turns ON while T1a, T2a, T2b, and TP4 along with the switches of all SS are OFF.
Mode-3: In this mode, Tb switches of both the SM, TP switches of all three SS, switches, TS and TP4 are turned OFF while Ta switches of both SM and TC switches of all three SS are ON. This switching arrangement connects all the SM's capacitors in series. Turning ON all the TC switches makes diodes of each SS forward-biased, causing all the capacitors of the SS to connect in parallel with each other and with the cluster of the series-connected SM's capacitors. This cluster of capacitors acts as a voltage source to the SS's capacitors and charges them at the multiples of VS. If there are x number of SM, then each SS's capacitor gets charged to x times VS. In case of HVMG consisting of two SM and three SS, each SS's capacitor, i.e., CSS1, CSS2, and CSS3 will be charge to 2VS. The equivalent circuit diagram of HVMG during this mode is illustrated in Figure 2(c).
Mode-4: Figure 2(d) illustrates the equivalent circuit diagram of HVMG during mode-4. The high voltage pulse discharge occurs in this mode. All the SM and SS capacitors are made to come in series with each other by turning ON, TP4, Ta switches of both SM, and TP switches of all SS. Simultaneously, Tb switches of both SM, TC switches of all SS, and switch TS are kept in an OFF state. If there are x number of SM and y number of SS, then the magnitude of the pulse (VPulse) is obtained as
V_Pulse=x(y+1)V_S
(1)
In the case of HVMG having two SM and three SS, magnitude of Vpulse is 8VS.
A. Steady-State Analysis
This section presents the steady-state analysis of the HVMG having two SM (x=2) and three SS (y=3). The following assumptions are considered in establishing this analysis:
(i) All the SM capacitors are identical (CSM1=CSM2=C1) and loss-less.
(ii) All the SS capacitors also have equal capacitance, i.e., CSS1=CSS2=CSS3=C2, and are loss-less.
(iii) All the switches and diodes are ideal.
(iv) The circuit is free from stray resistance, inductance, and capacitance.
The switching pattern and the steady-state voltage waveforms are provided in Figure 3, where i=1,2, j=1,2,3, and k=1,2,3,4.
The circuit has four modes of operation. In the first mode, CSM1 charges to input dc voltage level, VS. Then, in the second mode, CSM2 charges to VS. The time taken by each capacitor to get finally charged to VS is calculated using the following expression.
v_C1 (t)=(V_s-V_2 )[1-e^(((-t)/(r_limit C_1 )) ) ]+V_2 (2)
In mode-3, both the SS capacitors get charged twice of v1, i.e., v3. v1 is the voltage up to which both the SM capacitors discharge while charging the SS capacitors, and it is obtained as (1-ß)VS, where ß= permissible per unit dip in each SM capacitor's voltage. The minimum time required by SS capacitors to charge to v3 or the minimum time taken by the capacitors of SM to discharge to v1 is given below
t_u=(5xyr_limit C_1 C_2)/((C_1+xyC_2 ) ) (3)
where, rlimit= limiting resistor connected in series with SM capacitors to limit the peak inrush current. The peak inrush current, Ipk is found using: ßVS/rlimit. The rlimit should be chosen such that, Ipk should not exceed half of the rated switch current (safety margin=2).
The high voltage pulse having a magnitude equal to the sum of the standing voltage of all the SM and SS capacitors, i.e., x(y+1)VS, is generated in mode-4. However, its amplitude is a little less than the analytically predicted sum, and it is calculated as "[(1-ß)x(y+1)VS]". The output pulse voltage expression during this mode is given as
V_Pulse (t)=(1-ß)x(y+1) V_S e^[(-(xC_2+yC_1 )(t-t_3 ))/((R+xr_limit ) C_1 C_2 )] (4)
B. Capacitor Design Procedure
This section explains the procedure for the selection of the capacitors of the HVMG. The design procedure is elaborated with the help of a design example (VS=150 V, VPulse= 1.2 kV, switching frequency= 1 kHz, pulse-width= 50 µs, R= 5 k?). Before selecting the capacitors, the number of SM and SS required by the HVMG is to be known. For the above mentioned specifications, the number of SM and SS is calculated using Equation (1). If VS=150 V and VPulse= 1.2 kV, the following two combinations of x and y meet the desired specifications, such as "x=4, y=1", "x=2, y=3". However, based on the various parameters such as the device's voltage stresses and counts and switching frequency, an optimum number of SM and SS, i.e., "x=2, y=3," is chosen.
Since SS capacitors are charged by the SM capacitors hence, the amount of energy released by all the SM capacitors during the charging of SS capacitors is equal to the energy absorbed by all the SS capacitors, and it is provided below
xC_1(V_S^2-V_1^2)/2= yC_2(V_3^2-V_4^2)/2 (5)
If ß and ? are permissible per unit dip in each SM capacitor's voltage during mode-3 and each SS capacitor's voltage during mode-4, respectively. Then, "V1=(1-ß)VS", "V3=x(1-ß)VS", and "V4=x(1-ß)(1-?)VS". Putting all these expressions in Equation (5) gives the following relationship between C1 and C2.
C_1=xy(1- ß)^2[1-(1-?)^2]C_2/[1-(1- ß)^2] (6)
Rearrangement of Equation (4) gives
(xC_2+xC_1)/C_1C_2=(R+xr_limit){ln[(1- ß)x(y+1)V_S/V_Pulse(t)]}/t (7)
Using Equation (6) and (7), the capacitances of the SM and SS capacitors are calculated. For, ß=0.02, ?=0.02, rlimit=0.5 ?, and a permissible per unit dip of 0.04 in the pulsed amplitude, the value of C1 and C2 are obtained as 820 nF and 4.7 µF, respectively in the same design example.
C. Multipulse waveform generation
This sub-section illustrates how HVMG can generate the multipulse output waveform. A multipulse output waveform is the combination of wide and narrow high voltage pulses. To generate such kind of pulses from the HVMG, a slight change in the pulse discharge mode of the HVMG is required, the rest modes are kept the same.
In the pulse generation mode, HVMG can discharge its SS capacitors in different ways by adjusting the switching arrangements. One such arrangement to achieve a combination of wide and narrow high voltage pulses. This condition is met by discharging all the capacitors together during the pulse-width as illustrated in Figure 2(d) and preventing one or more capacitors from discharging into the load during a portion of the pulse-width as depicted in Figure 4. The equivalent circuit shown in Figure 4 is a sub-mode of the pulse generation mode. Here, one of the TP switches (TP2) is turned OFF to prevent CSS2 from discharging into the load. When TP2 is turned-OFF, diode D2 automatically becomes forward biased and completes the pulse discharging path, bypassing CSS2. During this sub-mode, the magnitude of the pulse becomes 6Vin, as CSS2, which holds the 2Vin voltage, is bypassed. This way the pulsed output can be seen as a combination of a wide high-voltage pulse with magnitude 6Vin and a narrow pulse with magnitude 8Vin (when CSS2 is not bypassed). Similarly, different patterns of the multipulse output can be obtained by allowing and preventing one or more capacitors from discharging during different portions of the pulse-width.
D. Experimental results:
To prove the feasibility of the concept, an experimental prototype of HVMG consisting of two SM and three SS is designed. The experimental parameters are provided in Table 1.
Figure 8 shows 50 µs wide pulses at a repetition rate of 1 kHz along with the source voltage. The magnitude of the pulse is found to be around 1.12 kV, which is a little less than the amplitude calculated using (1). It is due to the non-ideal nature of the experimental setup. The corresponding voltage waveforms of the SM capacitors and the SS capacitors, along with the output pulse, are provided in Figure 9 and Figure 10, respectively. All these results are in line with the analytical studies.
To prove the claim that HVMG can generate pulses at different repetition rates and variable widths, Figure 11 is presented, which shows 20 µs wide high voltage pulses repeating at a rate of 2000 pulses/second. A train of multipulse waveform is provided in Figure 12, where each multipulse output consists of two 30 µs pulses separated by a 20 µs pulse.

Table 1. Experimental parameters for the HVMG prototype.
Parameters Value/ Part no. Parameters Value/ Part no.
VS 150 V C1 6 µF
VPulse 1.2 kV C2 1 µF
Pulse rate 1 kHz-2 kHz Diodes DSEI 12-10A
Pulse size 20 µs- 50 µs Gate driver IC HCPL 3180
R 5 k? µ-controller dsPIC 30F6014A
SM switches IKW15T120 SS switches IGW15T120


, C , C , C , C , Claims:I Claim:
1. A high voltage solid-state pulsed power generator, comprising:
a dc voltage source (VS), a main switch (TS), a load switch (TP4), and multiple sub-modules (SM) and sub-stages (SS). A sub-module consists of a capacitor, a resistor, and two switches, whereas a sub-stage consists of a capacitor, a diode, and three switches. The switch herein refers to a controllable switch like MOSFET or an IGBT with anti-parallel diode.
2. The system as claimed in claim 1 is built by connecting the SM in series and then connecting the new formation in parallel with a cascaded structure formed by connecting the SS in parallel, wherein the positive side of VS is connected to the collector of TS, whose emitter is connected to the emitter of T1a, anode of D1, and collectors of T1b and TP1;
collector of T1a is connected to one terminal of the capacitor, CSM1 through a resistor, rlimit. The other terminal of CSM1 is connected to emitter of T1b, which is further connected with emitter of T2a and collector of T2b;
collector of T2a is connected to one terminal of the capacitor, CSM2 through a resistor, rlimit. The other terminal of CSM2 is connected to emitters of T2b and TC1, which is further connected with ground;
More number of similar SM can be inserted between the two SM by connecting the emitter of Taa of the SM to be inserted with the emitter of Ta-1b. Further, emitter of Tab need to be connected with the emitter of Ta+1a, herein, a is a positive natural number assigned to an SM. Additionally, these claims are made by considering the controllable switch as an IGBT with anti-parallel diode. Collector and emitter of this IGBT are to be read as drain and source, respectively in case of MOSFET as a controllable switch. Further, an external diode needs to be connected across the IGBT if it does not have an internal anti-parallel diode.
3. A sub-stage as claimed in claim 1 is developed by connecting anode of a diode, D (e.g. D1, D2, D3), with collector of TP (e.g. TP1, TP2, TP3), whose emitter is further connected with collector of TC (e.g. TC1, TC2, TC3), and one terminal of the capacitor, CSS, (e.g. CSS1, CSS2, CSS3), whose other terminal is connected with cathode of the diode of the same sub-stage.
4. Sub-stages as claimed in claim 1 are connected in parallel to build the system, herein to connect them in parallel, cathode of the diode and collector of TC of the initial stage is connected with the anode of the diode and emitter of TC of the next immediate stage, respectively. Multiple stages can be connected together in the same fashion.
5. The load switch as claimed in claim 1, herein, TP4 is connected between the cathode of the diode (herein, D3) of the last stage and the resistive load, R, whose other terminal is connected with the ground.
6. SM capacitors of claim 1, (e.g. CSM1, CSM2) are charged to the magnitude of the dc voltage source (VS) one after the other. Further, SM capacitors are brought in series to charge the SS capacitors (e.g. CSS1, CSS2, CSS3), wherein the charging path is completed through Ta switches (e.g. T1a, T2a) of SM, diodes (e.g. D1, D2, D3) of SS, and TC switches (e.g. TC1, TC2, TC3) of SS.
7. SS capacitors as mentioned in claim 1 are charged to the enhanced voltage level up to the maximum of xVS, wherein x is the number of SM used in the system;
SS capacitors can also be charged to a voltage level less than xVS, bypassing one or more SM capacitors of the structure. To bypass any SM capacitor of any module, Ta switch of the same SM need to be turned OFF. The SS capacitor charging path then gets completed through anti-parallel diode of the Tb switch of the bypassed SM.
8. The high voltage pulse is generated by discharging all the SM and SS capacitors together in series into the load, R;
The discharge path is completed through SM capacitors, Ta switches, and TP switches (e.g. TP1, TP2, TP3, and TP4).
9. A pulsed power generator capable of producing high-voltage unipolar pulse.
10. A high-voltage pulsed power generator capable of generating multipulse output suitable for food processing industry.
11. System claimed in claim 1 generated multipulse output by preventing one or more SS capacitors from discharging into the load during a portion of the pulse-width;
To bypass a sub-stage capacitor, TP switch of the same SS is turned OFF. This makes the diode of the same SS forward biased and completes the pulse discharging path. This causes the magnitude of the pulsed output to reduce by a value equal to the magnitude of the bypassed SS capacitor's voltage. Similarly, different patterns of the multipulse output are obtained by allowing and preventing one or more capacitors from discharging during different portions of the pulse-width.
12. The system provides flexibility in the adjustment of pulse magnitude, width, and repetition rate by controlling the flow of stored energy in its capacitors through controllable switches.


Dated this 31st day of October 2024

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