A DYNAMIC CLOCK DIVIDER FOR FRACTIONAL-N PHASE-LOCKED LOOP WITH SPREAD SPECTRUM CONTROL AND A METHOD

Abstract

A dynamic clock divider for fractional N phase locked loop with spread spectrum control and a method is disclosed. The dynamic clock divider features a chain of 2/3 divider cells capable of providing an output of a variable clock frequency based on a dynamically changing division factor. The dynamic clock divider incorporates a plurality of flip-flops ,multiplexers that facilitate the selection and latching of clock signals, ensuring stable and efficient operation. Additionally, a network of plurality of AND and OR gates dynamically enables or disables divider cells in response to inputs from a digital controller. The clock divider enables dynamic division range transitions, employing AND gates for increasing division factors and OR gates for decreasing them, enhancing overall flexibility from (2n to 2n+2 – 1). The dynamic clock divider also supports division range shifts(2n : 2n+2 - 1 to 2p : 2p+2 - 1) and efficiently manages transitions for operational adaptability. FIG. 1

Specification

Description:FIELD OF INVENTION
[0001] Embodiments of the present disclosure relate to the field of programmable clock divider in digital system and more particularly to a dynamic clock divider for fractional N phase locked loop with spread spectrum control and a method.

BACKGROUND
[0002] Traditionally, programmable clock divider circuits have been fundamental components in various digital systems, enabling the generation of clock signals at different frequencies by dividing an input clock signal. These circuits are widely used in applications ranging from microcontrollers to communication systems, where precise timing is essential. However, existing designs typically rely on fixed division factors that are set during programming, limiting their flexibility and responsiveness to dynamic changes in operational requirements. This static nature can hinder performance in environments where clock speed needs to adapt in real-time based on system demands.

[0003] Although there is notable progress in the field of programmable clock dividers and their adaptation in digital and communication systems there remains a significant gap in the dynamic variation and customized range of clock dividers. One of the primary limitations of conventional programmable clock dividers is their inability to accommodate dynamic adjustments to the division factor. When an attempt is made to change the division ratio on-the-fly, the output signal often deviates from the intended clock signal, resulting in timing inconsistencies that can adversely affect system performance. Additionally, traditional designs usually restrict the range of division factors to a narrow scope, typically from (2n to 2n+1 - 1). This constraint can prove problematic in applications requiring a broader spectrum of frequency adjustments, thereby necessitating a revaluation of existing architectures.

[0004] In response to these challenges, there exists a need to address these challenges and develop a more adaptable clock divider network and its interface. As technology advances, there is a growing interest in developing next-generation clock divider circuits capable of supporting dynamic division factors while maintaining signal integrity. The innovations in digital design, including integration of reconfigurable logic and adaptive mathematical model, hold promise for overcoming current limitations. These advancements aim to create circuits that can swiftly and accurately modify division factors in response to varying operational conditions, ultimately enhancing performance and versatility in diverse applications. The future clock dividers could provide more robust solutions for modern electronic systems that demand both precision and adaptability.

[0005] Hence, there is a need for an improved a dynamic clock divider for fractional N phase locked loop with spread spectrum control and a method which addresses the aforementioned issue(s).

OBJECTIVES OF THE INVENTION
[0006] The primary objective of the invention is to develop a dynamic clock divider circuit with an enhanced division range. In this invention, a chain of 2/3 divider cell along with an additional circuitry which serves as a control and functional logic of the dynamic clock divider is utilized to achieve the desired division factor for dynamic range. By utilizing digital logic configurations, the circuit allows for dynamic adjustments to the division factor, facilitating smooth transitions between different frequency ranges. This flexibility is essential for applications requiring real-time adaptations based on varying operational needs.

[0007] Another objective of the invention is to enable these dynamic changes, the architecture incorporates a combination of AND and OR gates that facilitate the bypassing of certain 2/3 divider cell based on the input division factor. When the division factor switches from a higher range to a lower range, OR gates are employed to bypass the corresponding plurality of 2/3 divider cell . Conversely, when transitioning from lower to higher ranges, AND gates activate the next cascaded plurality of 2/3 divider cell. This innovative switching mechanism ensures that the output clock signal remains stable and consistent, effectively preventing signal degradation that typically accompanies abrupt changes in division.

[0008] Yet another objective of the invention is to introduce a plurality of flip flops, a plurality of multiplexer and a digital controller configured to adapt as an additional circuitry .The first flip flop latches the division factor provided by the digital controller. The second flip flop is adapted to provide this latched division factor to the chain of 2/3 divider cells at the appropriate clock generated by the multiplexers. The first and the second flip-flops are controlled by a reset signal (srst) from the digital controller, which allows for the loading of the initial division factor during range switching. . This design not only enhances the functionality of the clock divider circuit but also integrates novel features that optimize its performance and adaptability in a variety of electronic applications.

[0009] Yet another objective of the invention is to introduce a solution adapted to support dynamic division range including shift within the range with division from (2n to 2n+2 - 1) and division range shifts(2n : 2n+2 - 1 to 2p to 2p+2 - 1) . The proposed solution allows for flexible adjustments to the division range, enabling shifts between ranges including internal switching in the range and overall range shift. This adaptability ensures that the system can accommodate varying data requirements and operational needs. The implementation focuses on maintaining performance and accuracy during these transitions. Overall, it provides a robust framework for dynamic range management in computational tasks.

BRIEF DESCRIPTION
[0010] In accordance with an embodiment of the present disclosure a dynamic clock divider for fractional N phase locked loop with spread spectrum control is provided. The dynamic clock divider includes an additional circuitry configured to enable the plurality of 2/3 divider cell to output an appropriate clock frequency for a continuously changing division factor to be utilized. The additional circuitry includes a plurality of flip flops comprising a first flip flop, a second flip flop and a third flip flop and a plurality of multiplexers including a first multiplexer and a second multiplexer. The dynamic clock divider also includes a plurality of AND gates and a plurality of OR gates adapted to adjust dynamically and perform plurality of function including enable and disable the plurality of 2/3 divider cells in response to receiving an input division factor from a digital controller. The digital controller is adapted to receive an input clock from a mod output of a most significant always on 2/3 divider cell. The most significant always on 2/3 divider cell includes the 2/3 divider cell providing an optimal duty cycle output. The first multiplexer is adapted to receive input signals from the mod outputs of the plurality of 2/3 divider cell and based on a select line the first multiplexer delivers the output ,wherein the output from the first multiplexer serves as a clock for the second flip flop, in response to a selection from the first multiplexer. The second multiplexer in cascade with the first multiplexer is adapted to receive the input signal from the output of first multiplexer and the mod output of the most significant always-on 2/3 divider cell. The first flip flop is configured to perform as a latch, wherein the first flop is adapted to receive an input clock from an inverted mod output of the most significant always-on 2/3 divider cell. The second flip flop is configured to send an output division factor to the plurality of 2/3 divider cells , wherein the second flip flop is adapted to receive an input clock from the output of the second multiplexer. The third flip flop is adapted to receive a reset pulse from the digital controller and its output serves as the select line for the second multiplexer, wherein the output of third flip flop is adapted to send out a signal to select an appropriate clock for the second flip flop. Additionally, the dynamic clock divider is adapted to combine an input to the plurality of AND gate with an output of the preceding 2/3 divider cell and the division factor from an additional circuit, wherein the additional circuit is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a clock signal. Furthermore, the dynamic clock divider includes the transition of the division factor from a lower range (2n to 2n+1 -1) to a higher range (2n+1 to 2n+2 -1), and the dynamic clock divider employs the plurality of AND gates to activate subsequent cascaded 2/3 divider cell. Moreover, the dynamic clock divider is adapted to shift the division factor from a higher range to lower ranges and the dynamic clock divider employs the plurality of OR gates to bypass the plurality of 2/3 divider cells range from a nth 2/3 divider cell to the most significant always-on 2/3 divider cell. Moreover, the dynamic clock divider is configured to enable the third flip flop by utilizing a srst signal from the digital controller as an input to the third flip flop wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges. Moreover, the dynamic clock divider is adapted to cascade the pair of multiplexers, including the first multiplexer enabled utilizing the mod outputs of most significant always-on 2/3 divider cell till mod count of the (n-1), and a static division reg as a select line for the first multiplexer ,wherein, the static division reg is the minimum number of the division factor range configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated . Moreover, the dynamic clock divider is configured to enable a second multiplexer within the pair of multiplexers to utilize the output from the first multiplexer , along with the mod output of the most significant always-on 2/3 divider cell and the output of the third flip-flop as the select line.

[0011] In accordance with another embodiment of the present disclosure a method for dynamic clock division for fractional N phase locked loop with spread spectrum control is provided. The method includes combining by an output of the preceding 2/3 divider cell and the division factor from the additional circuit as inputs to the plurality of AND gate, wherein the additional circuit is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a signal. The method also includes transitioning the division factor from a lower range to a higher range, the dynamic clock divider employs a plurality of AND gates to activate subsequent cascaded 2/3 divider cell. The method also includes shifting by the dynamic clock divider , the division factor from a higher range to lower ranges and employs the plurality of OR gates to bypass the plurality of 2/3 divider cells range from a nth 2/3 divider cell to the most significant always-on 2/3 divider cell. The method also includes enabling the third flip flop by utilizing a srst signal from the digital controller as an input to the third flip flop wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges. The method also includes cascading the pair of multiplexers, comprising the first multiplexer enabled utilizing the mod output of most significant always-on 2/3 divider cell till mod count of the (n-1), and a static division reg as a select line for the first multiplexer, wherein, the static division reg is the minimum number of the division factor range configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated . The method also includes enabling the second multiplexer within the pair of multiplexers to utilize the output from the first multiplexer , along with the mod output of the most significant always-on 2/3 divider cell and the output of the third flip-flop as a select line.

[0012] To further clarify the advantages and features of the present disclosure, a more particular description of the disclosure will follow by reference to specific embodiments thereof, which are illustrated in the appended figures. It is to be appreciated that these figures depict only typical embodiments of the disclosure and are therefore not to be considered limiting in scope. The disclosure will be described and explained with additional specificity and detail with the appended figures.

BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The disclosure will be described and explained with additional specificity and detail with the accompanying figures in which:

[0014] FIG. 1 is a schematic representation of the additional circuitry for control and functional logic of the dynamic clock divider for fractional N phase locked loop with spread spectrum control in accordance with an embodiment of the present disclosure;

[0015] FIG. 2 is a block diagram representation of a 2/3 divider cell chain for a dynamic clock divider for fractional N phase locked loop with spread spectrum control of FIG. 1, in accordance with an embodiment of the present disclosure; and

[0016] FIG. 3 illustrates a flow chart representing the steps involved in a method for a dynamic clock divider for fraction N phase locked loop with spread spectrum control in accordance with an embodiment of the present disclosure.

[0017] Further, those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and may not have necessarily been drawn to scale. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the figures by conventional symbols, and the figures may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the figures with details that will be readily apparent to those skilled in the art having the benefit of the description herein.

DETAILED DESCRIPTION
[0018] For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiment illustrated in the figures and specific language will be used to describe them. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Such alterations and further modifications in the illustrated system, and such further applications of the principles of the disclosure as would normally occur to those skilled in the art are to be construed as being within the scope of the present disclosure.

[0019] The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such a process or method. Similarly, one or more devices or sub-systems or elements or structures or components preceded by "comprises... a" does not, without more constraints, preclude the existence of other devices, sub-systems, elements, structures, components, additional devices, additional sub-systems, additional elements, additional structures, or additional components. Appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but not necessarily do, all refer to the same embodiment.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. The system, methods, and examples provided herein are only illustrative and not intended to be limiting.

[0021] In the following specification and the claims, reference will be made to a number of terms, which shall be defined to have the following meanings. The singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise.

[0022] In accordance with an embodiment of the present disclosure a dynamic clock divider for fractional N phase locked loop with spread spectrum control is provided. The dynamic clock divider includes an additional circuitry configured to enable the plurality of 2/3 divider cells to output an appropriate clock frequency for a continuously changing division factor to be utilized. The additional circuitry includes a plurality of flip flops comprising a first flip flop, a second flip flop and a third flip flop and a plurality of multiplexers including a first multiplexer and a second multiplexer. The dynamic clock divider also includes a plurality of AND gates and a plurality of OR gates adapted to adjust dynamically and perform plurality of function including enable and disable the plurality of 2/3 divider cells in response to receiving an input division factor from a digital controller. The digital controller is adapted to receive an input clock from a mod output of a most significant always on 2/3 divider cell. The most significant always on 2/3 divider cell includes the 2/3 divider cell providing an optimal duty cycle output. The first multiplexer is adapted to receive input signals from the mod outputs of the plurality of 2/3 divider cell and based on a select line the first multiplexer delivers the output ,wherein the output from the first multiplexer serves as a clock for the second flip flop, in response to a selection from the first multiplexer. The second multiplexer in cascade with the first multiplexer is adapted to receive the input signal from the output of first multiplexer and the mod output of the most significant always-on 2/3 divider cell. The first flip flop is configured to perform as a latch, wherein the first flop is adapted to receive an input clock from an inverted mod output of the most significant always-on 2/3 divider cell. The second flip flop is configured to send an output division factor to the plurality of 2/3 divider cells , wherein the second flip flop is adapted to receive an input clock from the output of the second multiplexer. The third flip flop is adapted to receive a reset pulse from the digital controller and its output serves as the select line for the second multiplexer, wherein the output of third flip flop is adapted to send out a signal to select an appropriate clock for the second flip flop. Additionally, the dynamic clock divider is adapted to combine an input to the plurality of AND gate with an output of the preceding 2/3 divider cell and the division factor from an additional circuit, wherein the additional circuit is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a clock signal. Furthermore, the dynamic clock divider includes the transition of the division factor from a lower range (2n to 2n+1 -1) to a higher range (2n+1 to 2n+2 -1), and the dynamic clock divider employs the plurality of AND gates to activate subsequent cascaded 2/3 divider cell. Moreover, the dynamic clock divider is adapted to shift the division factor from a higher range to lower ranges and the dynamic clock divider employs the plurality of OR gates to bypass the plurality of 2/3 divider cells range from a nth 2/3 divider cell to the most significant always-on 2/3 divider cell. Moreover, the dynamic clock divider is configured to enable the third flip flop by utilizing a srst signal from the digital controller as an input to the third flip flop wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges. Moreover, the dynamic clock divider is adapted to cascade the pair of multiplexers, including the first multiplexer enabled utilizing the mod outputs of most significant always-on 2/3 divider cell till mod count of the (n-1), and a static division reg as a select line for the first multiplexer ,wherein, the static division reg is the minimum number of the division factor range (i.e. 2n wherein range is 2n to 2n+2 -1) configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated . Moreover, the dynamic clock divider is configured to enable a second multiplexer within the pair of multiplexers to utilize the output from the first multiplexer , along with the mod output of the most significant always-on 2/3 divider cell and the output of the third flip-flop as the select line.

[0023] The dynamic clock divider for fractional N phase locked loop with spread spectrum control includes a voltage-controlled oscillator adapted to provide an input clock. The dynamic clock divider also includes a divide by N block including a plurality of 2/3 divider cells coupled to a plurality of AND gates and a plurality of OR gates , wherein the plurality of 2/3 divider cell includes a plurality of pair of transparent latches configured to be arranged diagonally, wherein a first pair of transparent latch are positive level triggered and a second pair of transparent latch are negative level triggered and the plurality of 2/3 divider cells are adapted to receive an input clock from the voltage-controlled oscillator.

[0024] FIG. 1 is a schematic representation of the additional circuitry for control and functional logic of the dynamic clock divider for fractional N phase locked loop with spread spectrum control in accordance with an embodiment of the present disclosure. The dynamic clock divider (200, Fig 2) includes an additional circuitry (230) configured to enable the plurality of 2/3 divider cell (240, Fig 2) to output an appropriate clock frequency for a continuously changing division factor to be utilized. The incorporation of an additional circuitry (230) allows the plurality of 2/3 divider cells (240, Fig 2) to adjust an output clock frequency and enable the output clock frequency to match the continuously varying division factor.

[0025] The dynamic clock divider (200, Fig 2) includes an additional circuitry (230), wherein the additional circuitry (230) includes a plurality of flip flops including a first flip flop (130), a second flip flop (140) and a third flip flop (150) and a plurality of multiplexers including a first multiplexer (110) and a second multiplexer (120).

[0026] Additionally, the dynamic clock divider (200, Fig 2) includes the plurality of AND gates (210, Fig 2) and the plurality of OR gates (220, Fig 2) adapted to adjust dynamically and perform plurality of function including enable and disable the plurality of 2/3 divider cells (240, Fig 2) in response to receiving an input division factor from a digital controller (160). The digital controller (160) adapted to receive an input clock from a mod output of a most significant always on 2/3 divider cell (240, Fig 2). The most significant always on 2/3 divider cell (240, Fig 2) includes the 2/3 divider cell (240, Fig 2) providing an optimal duty cycle output. The digital controller (160) is a circuit that manages the behaviour of a system utilizing digital signals. The digital controller (160) processes input data, applies control logic, and generates output signals to maintain desired performance. The duty cycle is the percentage of one period in which a signal is in ON state. The duty cycle is calculated as the ratio of the time the signal is ON to the total period of the signal, and often expressed as a percentage.

[0027] Additionally, the dynamic clock divider (200, Fig 2) includes the first multiplexer (110) adapted to receive input signals from the mod outputs of the plurality of 2/3 divider cell (240, Fig 2) and based on the select line the first multiplexer (110) delivers the output ,wherein the output from the first multiplexer (110) serves as a clock for the second flip flop (140) in response to a selection from the first multiplexer. The dynamic clock divider (200, Fig 2) also includes the second multiplexer (120) in cascade with the first multiplexer(110) and adapted to receive the input signal from the output of first multiplexer (110) and the output of the most significant always-on 2/3 divider cell (240, Fig 2). Additionally, the dynamic clock divider (200, Fig 2) includes the first flip flop (130) is configured to perform as a latch, wherein the first flop (130) is adapted to receive an input clock from an inverted mod output of the most significant always-on 2/3 divider cell (240, Fig 2). Furthermore, the dynamic clock divider (200, Fig 2) includes the second flip flop (140) configured to send an output division factor to the 2/3 divider cell (240, Fig 2), wherein the second flip flop (140) is adapted to receive an input clock from the output of the second multiplexer (120). Moreover, the dynamic clock divider (200, Fig 2) includes the third flip flop (150) is adapted to receive a reset pulse from the digital controller (160) and its output serves as a select line for the second multiplexer (120), wherein the output of third flip flop (150) is adapted to send out a signal to select an appropriate clock for the second flip flop (140).

[0028] Additionally, the dynamic clock divider (200, Fig 2) is adapted to combine an input to the plurality of AND gate (210, Fig 2) with an output of the preceding 2/3 divider cell (240, Fig 2) and the division factor from an additional circuit(230), wherein the additional circuit (230) is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a clock signal. The timing circuit is an electronic circuit designed to generate precise time intervals or control timing functions within a system. The timing circuits typically utilizes the plurality of flip flops adapted for synchronization. . The timing circuits are essential for synchronizing operations, controlling events, and managing time-dependent processes in devices including timers, clocks, and microcontrollers.

[0029] Additionally, the dynamic clock divider (200, Fig 2) is adapted to transition the division factor from a lower range to a higher range, the dynamic clock divider (200, Fig 2) employs the plurality of AND gates (210, Fig 2) to activate subsequent cascaded 2/3 divider cell (240, Fig 2). The dynamic clock divider (200, Fig 2) utilizes a range shift from a lower range (2n to 2n+1 -1) to a higher range (2n+1 to 2n+2 -1), wherein n is the represents the minimum number of 2/3 divider cells (240, Fig 2) required to perform a division by 2n.

[0030] Additionally, the dynamic clock divider (200, Fig 2) is adapted to shift the division factor from a higher range to lower ranges, the dynamic clock divider (200, Fig 2) employs the plurality of OR gates (220, Fig 2) to bypass the plurality of 2/3 divider cell (240, Fig 2) range from a nth 2/3 divider cell (240, Fig 2) to the most significant always-on 2/3 divider cell (240, Fig 2). The dynamic clock divider (200, Fig 2) is designed to bypass all the 2/3 divider cell (240, Fig 2) starting from a nth 2/3 divider cell (240, Fig 2) to the most significant always-on 2/3 divider cell (240, Fig 2), wherein the most significant always-on 2/3 divider cell (240, Fig 2) is a 3rd divider cell (240, Fig 2) for the designed circuitry among the plurality of 2/3 divider cell (240, Fig 2).

[0031] Additionally, the dynamic clock divider (200, Fig 2) includes enable the third flip flop (150) by utilizing a srst signal from the digital controller (160) as an input to the third flip flop (150) wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges. The reset signal is a control signal used to initialize or restore a system or a component to a known starting state. The reset signal when activated sets registers to pre-set values, and stops ongoing processes, ensuring reliable operation.

[0032] Additionally, the dynamic clock divider (200, Fig 2) is adapted to cascade the pair of multiplexers, including the first multiplexer (110) enabled utilizing the mod outputs of most significant always-on 2/3 divider cell (240, Fig 2) till mod count of the (n-1), and a static division reg as a select line for the first multiplexer (110),wherein, the static division reg is the minimum number of the division factor range i.e. 2n (wherein range is 2n to 2n+2 -1) configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated. A select line in the multiplexer determines which input signal is routed to the output. By receiving binary values, the select line effectively controls the switching mechanism, enabling the multiplexer to choose one of several input routed. The static division reg is designed to hold a programmed division factor that defines the minimum number of the range for division operations. This value is set and remains unchanged, ensuring consistent performance within the specified range during normal operation. The static division reg only updates when a reset pulse is generated , allowing for reconfiguration if needed.

[0033] Additionally, the dynamic clock divider (200, Fig 2) is adapted to enable the second multiplexer (120) within the pair of multiplexers to utilize the output from the first multiplexer (110), along with the mod output of the most significant always-on 2/3 divider cell (240, Fig 2) and the output of the third flip-flop (140) as a select line.

[0034] In one embodiment, the dynamic clock divider (200, Fig 2) is connected in a phase lock loop system wherein the phase lock loop system includes a voltage-controlled oscillator, a phase detector, a loop filter, the divide by N block including the plurality of 2/3 divider cell (240, Fig 2) , the additional circuit (230) to adjust the division factor received from the digital controller(160). A phase locked loop is an electronic control system that synchronizes an output signal phase with a reference signal phase. The phase locked loop includes mainly three main components including a phase detector, a low-pass filter, and a voltage-controlled oscillator The phase detector compares the phase of the input signal with the output signal, generating an error signal that is filtered and used to adjust the voltage-controlled oscillator frequency.

[0035] In one embodiment, the dynamic clock divider (200, Fig 2) includes a cascade of the plurality of 2/3 divider cell (240, Fig 2) , wherein, the plurality of 2/3 divider cell (240, Fig 2) receives a signal from the voltage-controlled oscillator and an adjusted division factor from an additional circuit (230). The internal structure of plurality of 2/3 divider cells (240, Fig 2) includes a pair of transparent latches configured to be arranged diagonally, wherein a first pair of transparent latches are positive level triggered and a second pair of transparent latches are negative level triggered. These latches are configured to utilize an input signal from the voltage-controlled oscillator.

[0036] In one embodiment, the dynamic clock divider (200, Fig 2) is adapted to allow the division factor to switch from one range to another range comprising the range switch from a higher to lower, a lower to higher range, and accordingly enables the one or more among the plurality of 2/3 divider cell (240, Fig 2). The range shift includes the lower range (2n to 2n+1 -1) to the higher range (2n+1 to 2n+2 -1) and the higher range (2n+1 to 2n+2 -1) to the lower range (2n to 2n+1 -1) and allow for flexible and seamless operation of device while switching.

[0037] In one embodiment, the dynamic clock divider (200,Fig 2) is adapted to utilize the range defined from 2n to 2(n+2)-1, wherein n represents the minimum number of 2/3 divider cell (240,Fig 2) required to perform a division by 2n . This adaptation allows the dynamic clock divider (200,Fig 2) to efficiently adjust its output frequency based on the required range.

[0038] In one embodiment, the dynamic clock divider (200,Fig 2) is configured and based on the input plurality of 2/3 divider cell (240,Fig 2) performs a division and propagate a signal to the next block. The input block processes the input clock by dividing it according to a specified factor, generating a modified clock signal. The resulting signal is then propagated to the next block , ensuring synchronized timing across elements.

[0039] In one embodiment, the dynamic clock divider (200, Fig 2) is configured to allow a dynamic change in the division factor. The dynamic clock divider (200, Fig 2) is designed with digital logic arrangements that enable real-time adjustments to the division factor. By utilizing control signals from external sources, the dynamic clock divider (200, Fig 2) can modify its division ratio as needed. This flexibility allows the system to respond to varying operational conditions or performance requirements. As a result, the output clock frequency can be dynamically tuned to optimize functionality without requiring a complete system reset.

[0040] In one embodiment, the dynamic clock divider (200, Fig 2) is adapted to generate a divided down representation of the input clock signal and result an output clock signal according to the dynamic division factor. The additional circuitry (230) is configured to enable the plurality of 2/3 divider cell (240, Fig 2) to output an appropriate clock frequency for a continuously changing division factor to be utilized. The additional circuitry (230) adjusts the division factor dynamically, allow for flexible changes in the output frequency based on specific operational needs.

[0041] In one embodiment, the dynamic clock divider (200, Fig 2) is configured to adapt to support dynamic division range including shift within the range with division from (2n to 2n+2 - 1) and division range shifts(2n : 2n+2 - 1 to 2p to 2p+2 - 1). The dynamic clock divider (200, Fig 2) allows for flexible adjustments to the division range, enabling shifts between ranges including internal switching in the range and overall range shift. This adaptability ensures that the dynamic clock divider ( 200, Fig 2) can accommodate varying data requirements and operational needs for dynamic range management in computational tasks.

[0042] FIG. 2 is a block diagram representation of a 2/3 divider cell chain for a dynamic clock divider for fractional N phase locked loop with spread spectrum control of FIG. 1, in accordance with an embodiment of the present disclosure. The dynamic clock divider (200) includes a divide by N block including the plurality of 2/3 divider cell (240) coupled to the plurality of AND gates (210) , the plurality of OR gates (220) and the additional circuitry (230) configured to enable the plurality of 2/3 divider cell (200) to output an appropriate clock frequency for a continuously changing division factor to be utilized.

[0043] For example, consider a scenario, a mobile phone needs to adjust its signal clock frequency for optimal power consumption while transmitting data. The dynamic clock divider (200, Fig 2) can quickly change the division factor, effectively lowering the output clock frequency to match the new data requirements. The device starts with a clock frequency of 800 MHz, utilizing a plurality of 2/3 divider cells (240, Fig 2) to output 100 MHz for regular operation. The digital controller (160) sends the required division factor to the dynamic clock divider (200, Fig 2) based on the current transmission mode. The first multiplexer (110) selects the clock output from the mod outputs of a specific 2/3 divider cell (240, Fig 2) based on the static div reg , feeding it into the second multiplexer (120). The first flip-flop (130) latches the selected signal and ensure stability, while the second flip-flop (140) updates the division factor for subsequent operations. When the device switches to a power-saving mode, the division factor changes to output a lower frequency such as 50 MHz .The plurality of AND gates (210, Fig 2) activate additional a plurality of 2/3 divider cells (240, Fig 2) as needed, while the plurality of OR gates (220, Fig 2) bypass all the non-significant 2/3 divider cells (240, Fig 2) to manage the transition between ranges efficiently. The third flip-flop (150) receives a reset pulse from the digital controller (160), ensuring that the appropriate clock source is selected during mode changes. The design incorporates spread spectrum techniques to reduce electromagnetic interference, enhancing overall signal quality.

[0044] FIG. 3 illustrates a flow chart representing the steps involved in a method for a dynamic clock divider for fraction N phase locked loop with spread spectrum control in accordance with an embodiment of the present disclosure. The method includes combining by an output of the preceding 2/3 divider cell and the division factor from the additional circuit as inputs to the plurality of AND gate, wherein the additional circuit is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a signal. The method also includes transitioning the division factor from a lower range to a higher range, the dynamic clock divider employs a plurality of AND gates to activate subsequent cascaded 2/3 divider cell. The method also includes shifting by the dynamic clock divider , the division factor from a higher range to lower ranges and employs the plurality of OR gates to bypass the plurality of 2/3 divider cell range from a nth 2/3 divider cell to the most significant always-on 2/3 divider cell. The method also includes enabling the third flip flop by utilizing a srst signal from the digital controller as an input to the third flip flop wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges. The method also includes cascading the pair of multiplexers, comprising the first multiplexer enabled utilizing the mod output of most significant always-on 2/3 divider cell till mod count of the (n-1), and a static division reg as a select line for the first multiplexer, wherein, the static division reg is the minimum number of the division factor range configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated .The method also includes enabling the second multiplexer within the pair of multiplexers to utilize the output from the first multiplexer , along with the mod output of the most significant always-on 2/3 divider cell and the output of the third flip-flop as a select line.

[0045] The method (300) includes combining by an output of the preceding 2/3 divider cell and the division factor from the additional circuit as inputs to the plurality of AND gate, wherein the additional circuit is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a signal in step (305).

[0046] The method (300) includes transitioning the division factor from a lower range to a higher range, the dynamic clock divider employs a plurality of AND gates to activate subsequent cascaded 2/3 divider cell in the step (310).

[0047] The method (300) includes shifting by the dynamic clock divider , the division factor from a higher range to lower ranges and employs the plurality of OR gates to bypass the plurality of 2/3 divider cell range from a nth 2/3 divider cell to the most significant always-on 2/3 divider cell in the step (315).

[0048] The method (300) includes enabling the third flip flop by utilizing a srst signal from the digital controller as an input to the third flip flop wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges in the step (320).

[0049] The method (300) includes cascading the pair of multiplexers, comprising the first multiplexer enabled utilizing the mod output of most significant always-on 2/3 divider cell till mod count of the (n-1), and a static division reg as a select line for the first multiplexer, wherein, the static division reg is the minimum number of the division factor range configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated in the step (325).

[0050] The method (300) includes enabling the second multiplexer within the pair of multiplexers to utilize the output from the first multiplexer , along with the mod output of the most significant always-on 2/3 divider cell and the output of the third flip-flop as a select line in the step (330).

[0051] Various embodiments of the dynamic clock divider for fractional-N phase-locked loop with spread spectrum control and a method described above enables various advantages. The dynamic clock divider (200, Fig 2) by incorporating a plurality of 2/3 divider cells (240, Fig 2), can dynamically adjust the output frequency to match varying operational demands, enhancing overall efficiency. The use of plurality of flip-flops including the first flip flop (130) , the second flip flop (140) and the third flip flop (150) ensures stable signal latching, allowing for quick and reliable updates to the division factor. Additionally , the plurality of multiplexers including the first multiplexer (110), and the second multiplexer (120) play a crucial role in selecting the appropriate clock sources, enabling seamless transitions between different frequencies based on real-time needs. This flexibility not only optimizes power consumption but also minimizes electromagnetic interference through spread spectrum techniques, making it ideal for communication applications. Furthermore, the integration of the plurality of AND gates (210, Fig 2) and the plurality of OR gates (220, Fig 2) allows for dynamic enabling and disabling of plurality of 2/3 divider cells (240, Fig 2), further enhancing adaptability. The dynamic clock divider (200, Fig 2) can efficiently handle transitions between lower and higher division ranges, ensuring precise timing and synchronization across operations. The dynamic clock divider (200, Fig 2) employs a digital controller (160) configured to provide an input division factor. The dynamic clock divider (200, Fig 2) can rapidly respond to changing conditions, significantly improving device performance. Overall, the dynamic clock divider(200, Fig 2) not only improves responsiveness and versatility but also enhances the overall robustness of clock management systems, making it a superior choice for modern digital circuits compared to previous static methods.

[0052] It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the disclosure and are not intended to be restrictive thereof.

[0053] While specific language has been used to describe the disclosure, any limitations arising on account of the same are not intended. As would be apparent to a person skilled in the art, various working modifications may be made to the method in order to implement the inventive concept as taught herein.

[0054] The figures and the foregoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts need to be necessarily performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples.
, Claims:. A dynamic clock divider (200) for fractional N phase locked loop with spread spectrum control comprising:
a voltage-controlled oscillator adapted to provide an input clock;

a divide by N block comprising a plurality of 2/3 divider cell (240) coupled to a plurality of AND gates (210) and a plurality of OR gates (220);

wherein the plurality of 2/3 divider cell (240) comprising a plurality of pair of transparent latches configured to be arranged diagonally, wherein a first pair of transparent latch are positive level triggered and a second pair of transparent latch are negative level triggered;

wherein the plurality of 2/3 divider cell (240) are adapted to receive an input clock from the voltage-controlled oscillator;

characterized in that,

an additional circuitry (230) configured to enable the plurality of 2/3 divider cell (240) to output an appropriate clock frequency for a continuously changing division factor to be utilized;

wherein the additional circuitry (230) comprises a plurality of flip flops comprising a first flip flop (130), a second flip flop (140) and a third flip flop (150) and a plurality of multiplexers comprising a first multiplexer (110) and a second multiplexer (120);

wherein the plurality of AND gates (210) and the plurality of OR gates (220) is adapted to adjust dynamically and perform plurality of function comprising enable and disable the plurality of 2/3 divider cells (240) in response to receiving an input division factor from a digital controller (160);
the digital controller (160) adapted to receive an input clock from a mod output of a most significant always on 2/3 divider cell (240);
wherein the most significant always on 2/3 divider cell (240) comprises the 2/3 divider cell (240) providing an optimal duty cycle output;
the first multiplexer (110) adapted to receive input signals from the mod output of the plurality of 2/3 divider cell (240) and based on the select line the first multiplexer (110) delivers the output ,wherein the output from the first multiplexer (110) serves as a clock for the second flip flop (140) in response to a selection from the first multiplexer (110);
the second multiplexer (120) in cascade with the first multiplexer(110) is adapted to receive the input signal from the output of first multiplexer (110) and the mod output of the most significant always-on 2/3 divider cell (240);

the first flip flop (130) is configured to perform as a latch, wherein the first flop (130) is adapted to receive an input clock from an inverted mod output of the most significant always-on 2/3 divider cell (240);

the second flip flop (140) is configured to send an output division factor to the plurality of 2/3 divider cell (240), wherein the second flip flop (140) is adapted to receive an input clock from the output of the second multiplexer (120);

the third flip flop (150) is adapted to receive a reset pulse from the digital controller (160) and its output serves as a select line for the second multiplexer (120), wherein the output of third flip flop (150) is adapted to send out a signal to select an appropriate clock for the second flip flop (140);
combine an input to the plurality of AND gate (210) with an output of the preceding 2/3 divider cell (240) and the division factor from an additional circuit(230), wherein the additional circuit (230) is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a clock signal;
transition the division factor from a lower range to a higher range, the dynamic clock divider (200) employs the plurality of AND gates (210) to activate subsequent cascaded 2/3 divider cell (240) ;
shift the division factor from a higher range to lower ranges, the dynamic clock divider (200) employs the plurality of OR gates (220) to bypass the plurality of 2/3 divider cell (240) range from a nth 2/3 divider cell (240) to the most significant always-on 2/3 divider cell (240) ;
enable the third flip flop (150) by utilizing a srst signal from the digital controller (160) as an input to the third flip flop (150) wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges;
cascade the pair of multiplexers, comprising the first multiplexer (110) enabled utilizing the mod outputs of most significant always-on 2/3 divider cell (240) till mod count of the (n-1), and a static division reg as a select line for the first multiplexer (110) ,wherein, the static division reg is the minimum number of the division factor range configured to be a programmed value and adapted to remain static for a specific range until a reset pulse is generated ; and
enable the second multiplexer (120) within the pair of multiplexers to utilize the output from the first multiplexer (110), along with the mod output of the most significant always-on 2/3 divider cell (240) and the output of the third flip-flop (140) as a select line.

2. The dynamic clock divider (200) as claimed in claim 1, connected in a phase lock loop system wherein the phase lock loop system comprises a voltage-controlled oscillator, a phase detector, a loop filter, the divide by N block comprising the plurality of 2/3 divider cell (240) the additional circuit (230) to adjust the division factor received from the digital controller(160).
3. The dynamic clock divider (200) as claimed in claim 1, comprises a cascade of the plurality of 2/3 divider cell (240) , wherein, the plurality of 2/3 divider cell (240) receives a signal from the voltage-controlled oscillator and an adjusted division factor from an additional circuit (230).
4. The dynamic clock divider (200) as claimed in claim 1 allows the division factor to switch from one range to another range comprising the range switch from a higher to lower, a lower to higher range, and accordingly enables the one or more among the plurality of 2/3 divider cell (240).
5. The dynamic clock divider (200) as claimed in claim 1, utilizes the range defined from 2m to 2(m+2)-1, wherein m represents the minimum number of 2/3 divider cell (240) required to perform a division by 2m .
6. The dynamic clock divider (200) as claimed in claim 1, based on the input plurality of 2/3 divider cell (240) performs a division and propagate a signal to the next block.
7. The dynamic clock divider (200) as claimed in claim 1, is configured to allow a dynamic change in the division factor.
8. The dynamic clock divider (200) as claimed in claim 1, generates a divided down representation of the input clock signal adapted to result in an output clock signal according to the dynamic division factor.
9. The dynamic clock divider (200) as claimed in claim 1,is configured to adapt to support dynamic division range including shift within the range with division from (2n to 2n+2 - 1) and division range shifts(2n : 2n+2 - 1 to 2p to 2p+2 - 1).

10. A method (300) for dynamic clock division for fraction N phase locked loop with spread spectrum control comprising :
combining by an output of the preceding 2/3 divider cell and the division factor from the additional circuit as inputs to the plurality of AND gate , wherein the additional circuit is also configured to adapt as a timing circuit to synchronize an operation and ensure accurate timing for a signal;(305)
transitioning the division factor from a lower range to a higher range, the dynamic clock divider employs a plurality of AND gates to activate subsequent cascaded 2/3 divider cell; (310)
shifting by the dynamic clock divider , the division factor from a higher range to lower ranges and employs the plurality of OR gates to bypass the plurality of 2/3 divider cell range from a nth 2/3 divider cell to the most significant always-on 2/3 divider cell; (315)
enabling the third flip flop by utilizing a srst signal from the digital controller as an input to the third flip flop wherein, the srst signal is a pulse signal used to load the initial division factor while switching ranges; (320)
cascading the pair of multiplexers, comprising the first multiplexer enabled utilizing the mod output of most significant always-on 2/3 divider cell till mod count of the (n-1), and a static division reg as a select line for the first multiplexer, wherein, the static division reg is the minimum number of the division factor range configured to be a registered programmed value and adapted to remain static for a specific range until a reset pulse is generated ; (325) and
enabling the second multiplexer within the pair of multiplexers to utilize the output from the first multiplexer , along with the mod output of the most significant always-on 2/3 divider cell and the output of the third flip-flop as a select line. (330)

Dated this 28th day of October 2024

Signature

Jinsu Abraham
Patent Agent (IN/PA-3267)
Agent for the Applicant